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參數(shù)資料
| 型號： | TPS2340APFPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP80 |
| 封裝： | GREEN, PLASTIC, HTQFP-80 |
| 文件頁數(shù)： | 4/29頁 |
| 文件大?。?/td> | 578K |
| 代理商： | TPS2340APFPRG4 |
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TPS2340A
SLUS528A MARCH 2002 REVISED AUGUST 2002
12
www.ti.com
APPLICATION INFORMATION
power cycling and PME
The PCI Power Management Specification defines a signal called PME (power management event) to allow
power management events to be communicated back to the system. The TPS2340A provides a slot-specific
PMEx input and a gated PMEO output pin that is monitored by the system. The gated PMEO output is controlled
by the SWx slot switch similar to the 3.3-Vaux supply pins described above, but with a delay during connection
as shown below. The purpose of the delay is to ensure that 3.3-Vaux power is stable to the slot before connecting
the PMEx signal. (If the device were to observe the PMEx signal while 3.3-Vaux power was still ramping up, a
false trigger could result.)
The 3.3-Vaux circuitry provides short-circuit fault detection. In the event of a fault, the slot 3.3-Vaux and PME
signals are immediately disconnected. The fault state is latched internally in the TPS2340A and is cleared by
opening the SWx slot switch or by the removal of the 3.3-Vaux power supplying the TPS2340.
PME ENABLE
10 ms
TYP
2.5 ms
TYP
10 ms
TYP
UDG01016
SWx
3VAUXx
Auxfltx
Figure 2. 3.3Vaux and PME Gating
When SWx is closed, 3VAUXx power is immediately applied to the slot with controlled slew rate, minimizing
inrush current into 3VAUXx bypass capacitors. After 3VAUXx power is above threshold, a delay timer starts.
At the end of the delay timer cycle, the PMEx switches close, allowing connection of the PMEx signal to the
PMEO output. When multiple TPS2340A devices are used in a system, the PMEO output pins can be connected
to the same node, creating a wiredOR PME bus that can be connected to a system interrupt input.
When SWx is opened or if there is a power fault on channel x, the PMEx switch for that channel is immediately
opened and the 3VAUXx power for that channel is removed. Although these events happen at approximately
the same time, the 3VAUXx power should remain high until the PMEx switch is open so that falling 3VAUXx
power doesn’t cause a nuisance PMEx interrupt. To insure that 3VAUXx remains high during a power fault,
3VAUXx should have a bypass capacitance of at least 20
F. If the capacitor is not available on the inserted
card, it should be provided on the system board.
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