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參數(shù)資料
| 型號： | TPS2306DWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大小： | 427K |
| 代理商： | TPS2306DWG4 |
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TPS2306
DUAL SEQUENCING HOT SWAP POWER MANAGER
SLVS368 APRIL 2001
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
charge pump and housekeeping
The TPS2306 contains an on-chip high-voltage charge pump circuit to step up the supply potential at the VCC
input to provide the gate drive for external N-channel devices. A capacitor with a value between 0.01
F and
0.1
F must be connected from the CPUMP pin to ground to provide additional energy storage on the charge
pump output.
During a start-up sequence, undervoltage lockout (UVLO) comparators monitor the supply levels at the
VCC/CS1 and CS2 pins, as well as the charge pump output. The LCAs are inhibited, and the GATEx outputs
pulled low, until input and charge pump levels exceed the UVLO threshold levels. This ensures sufficient supply
potential for the device and LCAs for predictable sequencing control, fault detection, and gate drive prior to
turning the outputs on. The VCC/CS1 input UVLO threshold has a maximum specification of 2.9 V to ensure
start-up, down to the minimum recommended operating supply of 4.0 V. The CS2 input starts with a 2.75-V input
level. There is a nominal amount of hysteresis on the input thresholds to guard against repeated starts in
response to supply droop. The charge pump UVLO threshold is set for a nominal 12.5 V with a VCC input of 5 V.
fault timer
The fault timer block contains the control circuitry for generating a time delay, which determines how long the
TPS2306 is allowed to operate in the constant-current, or linear, mode. Without the timer, fault conditions such
as starting up into a shorted load, would cause the TPS2306 to operate in the constant-current mode indefinitely,
at the programmed IMAX sourcing level. Conversely, the HSPM must allow sourcing long enough to charge the
input bulk capacitance. The determination of the time period needed depends on several factors, including:
1) the amount of capacitance to be charged, 2) the load characteristic (constant-current or resistive), and 3) the
soft-start characteristic, if used. Information about estimating the required timeout period is provided in the
Application Information section.
The fault time-out needed is the total ramp-up time of the two channel outputs.
Setting of the user-programmable time-out period is accomplished by connecting a capacitor between the
device CT pin and ground. When either of the linear amplifiers is operating in constant-current mode, circuitry
in the MODE/STATUS block generates the corresponding linear mode detected (LMDx) signal, starting the
timer. The timer operates by sourcing a nominal 50-
A from the CT pin, charging the external capacitor from
0 V. If output charging completes prior to time-out, the LCA’s drive to the rail, and load sourcing continues
uninterrupted. However, if the constant-current mode persists until the timing capacitor voltage exceeds the
1.5-V fault threshold, the TIMEOUT signal is latched as the shutdown signal (SD in the block diagram). Both
FET switches are turned off, and the FAULT output remains asserted.
To restart from a fault timeout, either the ENBL input must be toggled LO then HI, or device power must be
cycled.
enable input
The ENBL input allows host or remote turn-on and turn-off of the controlled supplies. Pulling this pin below 0.8 V
disables both external NMOS devices, and puts the IC in low-power sleep mode. Driving this pin above 2.0 V
enables the supply outputs. Because of the level translation circuitry at the ENBL input, this pin may be pulled
up externally to the VCC rail. As seen in the block diagram, assertion of the sleep mode (SLP) signal turns off
much of the peripheral circuitry of the device, including the charge pump, references, LCAs and overcurrent
comparators, reducing supply current to only 40
A typical with VCC = 12 V. In order to ensure controlled
shutdown according to the configured sequencing scheme, the gate potential of each output is monitored by
the MODE/STATUS circuitry. Once both gates have discharged below 1 V, the gate low detect (GLDx) signals
allow the part to enter sleep mode.
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