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參數(shù)資料
| 型號： | TPS2300IPWG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 644K |
| 代理商： | TPS2300IPWG4 |
www.ti.com
DETAILED DESCRIPTION
SLVS275G – FEBRUARY 2000 – REVISED NOVEMBER 2006
Table 1. Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
ISET1
15
I
Adjusts circuit-breaker threshold with resistor connected to IN1
ISET2
14
I
Adjusts circuit-breaker threshold with resistor connected to IN2
PWRGD1
17
O
Open-drain output, asserted low when VSENSE1 voltage is less than reference.
PWRGD2
13
O
Open-drain output, asserted low when VSENSE2 voltage is less than reference.
TIMER
4
O
Adjusts circuit-breaker deglitch time
VREG
5
O
Connects to bypass capacitor, for stable operation
VSENSE1
7
I
Power-good sense input channel 1
VSENSE2
6
I
Power-good sense input channel 2
DISCH1, DISCH2 – DISCH1 and DISCH2 should be connected to the sources of the external N-channel
MOSFET transistors connected to GATE1 and GATE2, respectively. These pins discharge the loads when the
MOSFET transistors are disabled. They also serve as reference-voltage connections for internal gate
voltage-clamp circuitry.
ENABLE or ENABLE – ENABLE for TPS2310 is active-low. ENABLE for TPS2311 is active-high. When the
controller is enabled, both GATE1 and GATE2 voltages will power up to turn on the external MOSFETs. When
the ENABLE pin is pulled high for TPS2310 or the ENABLE pin is pulled low for TPS2311 for more than 50 s,
the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to
discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see
VREG) when enabled and shuts down PREREG when disabled so that total supply current is less than 5
A.
FAULT – FAULT is an open-drain overcurrent flag output. When an overcurrent condition in either channel is
sustained long enough to charge TIMER to 0.5 V, both channels latch off and pull this pin low. In order to turn
the device back on, either the enable pin has to be toggled or the input power has to be cycled.
GATE1, GATE2 – GATE1 and GATE2 connect to the gates of external N-channel MOSFET transistors. When
the device is enabled, internal charge-pump circuitry pulls these pins up by sourcing approximately 15
A to
each. The turnon slew rates depend upon the capacitance present at the GATE1 and GATE2 terminals. If
desired, the turnon slew rates can be further reduced by connecting capacitors between these pins and ground.
These capacitors also reduce inrush current and protect the device from false overcurrent triggering during
powerup. The charge-pump circuitry generates gate-to-source voltages of 9 V–12 V across the external
MOSFET transistors.
IN1, IN2 – IN1 and IN2 should be connected to the power sources driving the external N-channel MOSFET
transistors connected to GATE1 and GATE2, respectively. The TPS2310/TPS2311 draws its operating current
from IN1, and both channels remains disabled until the IN1 power supply has been established. The IN1
channel has been constructed to support 3-V, 5-V, or 12-V operation, while the IN2 channel has been
constructed to support 3-V or 5-V operation
ISENSE1, ISENSE2, ISET1, ISET2 – ISENSE1 and ISENSE2, in combination with ISET1 and ISET2, implement
overcurrent sensing for GATE1 and GATE2. ISET1 and ISET2 set the magnitude of the current that generates
an overcurrent fault, through external resistors connected to ISET1 and ISET2. An internal current source draws
50
A from ISET1 and ISET2. With a sense resistor from IN1 to ISENSE1 or from IN2 to ISENSE2, which is
also connected to the drains of external MOSFETs, the voltage on the sense resistor reflects the load current.
An overcurrent condition is assumed to exist if ISENSE1 is pulled below ISET1 or if ISENSE2 is pulled below
ISET2.
PWRGD1, PWRGD2 – PWRGD1 and PWRGD2 signal the presence of undervoltage conditions on VSENSE1
and VSENSE2, respectively. These pins are open-drain outputs and are pulled low during an undervoltage
condition. To minimize erroneous PWRGDx responses from transients on the voltage rail, the voltage sense
circuit incorporates a 20-s deglitch filter. When VSENSEx is lower than the reference voltage (about 1.23 V),
PWRGDx is active low to indicate an undervoltage condition on the power-rail voltage. PWRGDx may not
correctly report power conditions when the device is disabled, because there is no gate drive power for the
PWRGD output transistor in the disable mode, or, in other words, PWRGD is floating. Therefore, PWRGD is
pulled up to its pullup power supply rail in disable mode.
3
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