參數(shù)資料
型號: TPS2226APWPRG4
廠商: Texas Instruments, Inc.
英文描述: CARDBUS POWER-INTERFACE SWITCHES FOR SERIAL PCMCIA CONTROLLERS
中文描述: CARDBUS功率接口開關(guān)用于串行PCMCIA控制器
文件頁數(shù): 3/29頁
文件大?。?/td> 447K
代理商: TPS2226APWPRG4
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
TPS2220A, TPS2223A
TPS2224A, TPS2226A
SLVS428B–MAY 2002–REVISED SEPTEMBER 2004
TPA222xA
–0.3 to 5.5
–0.3 to 5.5
–0.3 to 14
–0.3 to 6
–0.3 to 6
–0.3 to 14
See Dissipation Rating Table
Internally Limited
Internally Limited
–40 to 100
–55 to 150
260
10
UNIT
V
V
V
V
V
V
V
I(3.3V)
V
I(5V)
V
I(12V)(2)
V
I
Input voltage range for card power
Logic input/output voltage
V
O(xVCC)
V
O(xVPP)
V
O
Output voltage
Continuous total power dissipation
I
O(xVCC)
I
O(xVPP)
I
O
Output current
T
J
T
stg
Operating virtual junction temperature range
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds)
OC sink current
°
C
°
C
°
C
mA
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Not applicable for TPS2223A
(2)
T
25
°
C
POWER RATING
890 mW
1095 mW
3322 mW
DERATING FACTOR
ABOVE T
A
= 25
°
C
8.9 mW/
°
C
10.95 mW/
°
C
33.22 mW/
°
C
T
= 70
°
C
POWER RATING
489 mW
602 mW
1827 mW
T
= 85
°
C
POWER RATING
356 mW
438 mW
1329 mW
PACKAGE
(1)
24
30
24
DB
PWP
(1)
These devices are mounted on an JEDEC low-k board (2-oz. traces on surface).
MIN
MAX
3.6
5.5
13.5
UNIT
V
I(3.3V)(1)
V
I(5V)
V
I(12V)(2)
I
O(xVCC)
at T
J
= 100
°
C
I
O(xVPP)
at T
J
= 100
°
C
3
3
7
Input voltage, V
is required for all circuit
operations. 5V and 12V are only required for
their respective functions.
V
1
A
I
O
Output current
100
2.5
mA
MHz
f
(clock)
Clock frequency
Data
Latch
Clock
Reset
200
250
100
100
100
100
100
250
t
w
Pulse duration
ns
t
h
t
su
t
d(latch)
t
d(clock)
Data-to-clock hold time (see Figure 2)
Data-to-clock setup time (see Figure 2)
Latch delay time (see Figure 2)
Clock delay time (see Figure 2)
Operating virtual junction temperature (maximum to be calculated at worst case P
D
at 85
°
C
ambient)
ns
ns
ns
ns
T
J
–40
100
°
C
(1)
(2)
It is understood that for V
< 3 V, voltages within the absolute maximum ratings applied to pin 5V or pin 12V do not damage the IC.
Not applicable for TPS2223A
3
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