參數(shù)資料
型號(hào): TPS2148IDGNR
廠商: Texas Instruments, Inc.
英文描述: Analog IC
中文描述: 模擬IC
文件頁數(shù): 5/18頁
文件大?。?/td> 251K
代理商: TPS2148IDGNR
TPS2148
TPS2158
SLVS373
AUGUST 2001
5
www.ti.com
electrical characteristics over recommended operating junction-temperature range,
2.9 V
V
I(VIN/SWIN1)
5.5 V, V
I(ENx)
= 0 V, V
I(LDO_EN)
= 5 V, C
L(LDO_OUT)
= 10
μ
F,
T
J
=
40
°
C to 100
°
C (unless otherwise noted)
3.3 V LDO
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage, dc
VI(VIN/SWIN1) = 4.25 V to 5.25 V,
IO(LDO_OUT) = 0.5 mA to 200 mA
VI(VIN/SWIN1) = 3.2 V, IO = 200 mA, IO(OUT) = 150
mA
3.20
3.3
3.40
V
Dropout voltage
0.35
V
Line regulation voltage (see Note 1)
VI(VIN/SWIN1) = 4.25 V to 5.25 V, IO(LDO_OUT) = 5
mA
0.1
%/V
Load regulation voltage (see Note 1)
VI(VIN/SWIN1) = 4.25 V, IO(LDO_OUT) = 5 mA to 200
mA
0.4
1%
IOS
Short-circuit current limit
VI(VIN/SWIN1) = 4.25 V, LDO_OUT connected to
GND
0.275
0.33
0.55
A
Ilkg(R)
Reverse leakage current into
LDO_OUT
VO(LDO_OUT) = 3.3 V, VI(VIN/SWIN1) = 0 V,
VI(LDO_EN) = 0 V
VO(LDO_OUT) = 5.5 V, VI(VIN/SWIN1) = 2.7 V,
VI(LDO_EN) = 0 V
f = 1 kHz, CL(LDO_OUT) = 4.7
μ
F, ESR = 0.25
, IO =
5 mA, VI(VIN/SWIN1)p
p = 100 mV
10
μ
A
10
μ
A
Power supply rejection
50
dB
ton
Turnoff time, LDO_EN
transitioning low (see Note 1)
RL = 16
, CL(LDO_OUT) = 10
μ
F
0.25
1
ms
toff
Turnon time, LDO_EN
transitioning high (see Note 1)
RL = 16
, CL(LDO_OUT) = 10
μ
F
0.1
1
ms
Ramp-up time, LDO_OUT (0% to 90%)
VI(LDO_EN) = 5 V, VIN ramping up from 10% to 90%
in 0.1 ms, RL = 16
, CL(LDO_OUT) = 10
μ
F
0.1
1
ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTE 1. Specified by design, not tested in production.
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