
TPS2074, TPS2075
FOUR-PORT USB HUB POWER CONTROLLERS
SLVS288A
–
SEPTEMBER 2000
–
REVISED FEBRUARY 2001
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range,
4.5 V
≤
V
I(BP)
≤
5.5 V, 4.85 V
≤
V
I(SP)
≤
5.5 V, ENx = 0 V, BP_DIS = 0 V, C
L(3.3V_OUT)
= 10
μ
F (unless
otherwise noted)
internal voltage regulator
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VO
Output voltage, dc
VI(BP) = 4.25 V to 5.5 V,
IO = 100 mA
VI(BP) = 4.25 V to 5.25 V, IO= 5 mA
VI(BP) = 4.25 V,
VI(BP) = 4.25 V, 3.3V_OUT connected to GND
VI(3.3V_OUT) = 3.3 V
VI(3.3V_OUT) = 1 V
F = 1 kHz, CL(3.3V_OUT)=4.7
μ
F, ESR=0.25
,
IO=5 mA, VI(BP)PP=100 mV
IO= 5 mA to 100 mA
3.2
3.3
3.4
V
Dropout voltage
0.6
V
Line regulation
0.1
%/v
Load regulation
Short-circuit current limit
IO= 5 mA to 100 mA
0.6%
IOS
0.12
0.2
0.3
A
Pulldown transistor at 3.3V_OUTPUT
(see Note 1)
10
mA
5
PSRR
Power-supply ripple rejection (see Note 1)
40
dB
Low-level trip threshold voltage at PG
2.88
2.94
3
V
Vhys
VOH
VOL
Vref
Hysteresis voltage at PG (see Note 1)
50
100
mV
High-level output voltage at PG
4.25 V
≤
VI(BP)
≤
5.25 V, IO = 2 mA
4.25 V
≤
V
I
(BP)
≤
5.25 V, IO = 3.2 mA
2.4
V
Low-level output voltage at PG
0.4
V
Reference voltage at PG_DLY
1.22
V
μ
A
ms
Charge current at PG_DLY
3
td
Delay time at PG (see Notes 1 and 2)
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
NOTES:
1. Specified by design, not tested in production.
2. The PG delay time (td) is calculated using the PG_DLY reference voltage and charge current:
CL(PG_DLY) = 0.47
μ
F
190
td
CL(PG_DLY)
Charge Current
Vref
power switch timing requirements
PARAMETER
TEST CONDITIONS
VI(BP) = 5 V, VI(SP) = open, TA = 25
°
C,
CL = 100
μ
F, RL = 50
VI(SP) = VI(BP) = 5 V, TA = 25
°
C,
CL = 100
μ
F, RL = 10
VI(BP) = 5 V, VI(SP) = open, TA = 25
°
C,
CL = 100
μ
F, RL = 50
VI(SP) = VI(BP) = 5 V, TA = 25
°
C,
CL = 100
μ
F, RL = 10
VI(BP) = 5 V, VI(SP) = open, TA = 25
°
C,
CL = 100
μ
F, RL = 50
VI(SP) = VI(BP) = 5 V, TA = 25
°
C,
CL = 100
μ
F, RL = 10
VI(BP) = 5 V, VI(SP) = open, TA = 25
°
C,
CL = 100
μ
F, RL = 50
VI(SP) = VI(BP) = 5 V, TA = 25
°
C,
CL = 100
μ
F, RL = 10
MIN
TYP
MAX
UNIT
ton
Turnon time (see Note 1)
BP to OUTx
switch
4.5
ms
SP to OUTx
switch
4.5
tff
toff
Turnoff time (see Note 1)
BP to OUTx
switch
15
ms
SP to OUTx
switch
10
tr
Rise time output (see Note 1)
Rise time, output (see Note 1)
BP to OUTx
switch
4
ms
SP to OUTx
switch
3
tf
Fall time output (see Note 1)
Fall time, output (see Note 1)
BP to OUTx
switch
10
ms
SP to OUTx
switch
3
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
All BP to OUTx , SP to OUTx switches and the internal 3.3-V voltage regulator are loaded to the recommended continuous current rating of
100 mA, 500 mA and 100 mA, respectively, for the static drain-source on-state resistance measurements.
NOTE 1. Specified by design, not tested in production.