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參數(shù)資料
| 型號(hào)： | TPA6021A4NE4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PDIP20 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS001-AD, DIP-20 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大?。?/td> | 1823K |
| 代理商： | TPA6021A4NE4 |
www.ti.com
ROUT+
Device Shutdown
ROUT+
Device Shutdown
TPA6021A4
SLOS465 – JUNE 2005
When the FADE input is a logic low, the device is placed into fade-on mode. A logic high on this pin places the
amplifier in the fade-off mode. The voltage trip levels for a logic low (VIL) or logic high (VIH) can be found in the
recommended operating conditions table.
When a logic low is applied to the FADE pin and a logic low is then applied on the SHUTDOWN pin, the channel
gain steps down from gain step to gain step at a rate of two clock cycles per step. With a nominal internal clock
frequency of 58 Hz, this equates to 34 ms (1/29 Hz) per step. The gain steps down until the lowest gain step is
reached. The time it takes to reach this step depends on the gain setting prior to placing the device in shutdown.
For example, if the amplifier is in the highest gain mode of 20 dB, the time it takes to ramp down the channel
gain is 1.05 seconds. This number is calculated by taking the number of steps to reach the lowest gain from the
highest gain, or 31 steps, and multiplying by the time per step, or 34 ms.
After the channel gain is stepped down to the lowest gain, the amplifier begins discharging the bypass capacitor
from the nominal voltage of VDD/2 to ground. This time is dependent on the value of the bypass capacitor. For a
0.47-F capacitor that is used in the application diagram in Figure 19, the time is approximately 500 ms. This
time scales linearly with the value of bypass capacitor. For example, if a 1-F capacitor is used for bypass, the
time period to discharge the capacitor to ground is twice that of the 0.47-F capacitor, or 1 second. Figure 22
below is a waveform captured at the output during the shutdown sequence when the part is in fade-on mode.
The gain is set to the highest level and the output is at VDD when the amplifier is shut down.
When a logic high is placed on the SHUTDOWN pin and the FADE pin is still held low, the device begins the
start-up process. The bypass capacitor will begin charging. Once the bypass voltage reaches the final value of
VDD/2, the gain increases in 2-dB steps from the lowest gain level to the gain level set by the dc voltage applied
to the VOLUME pin.
In the fade-off mode, the output of the amplifier immediately drops to VDD/2 and the bypass capacitor begins a
smooth discharge to ground. When shutdown is released, the bypass capacitor charges up to VDD/2 and the
channel gain returns immediately to the value on the VOLUME terminal. Figure 23 below is a waveform captured
at the output during the shutdown sequence when the part is in the fade-off mode. The gain is set to the highest
level, and the output is at VDD when the amplifier is shut down.
The power-up sequence is different from the shutdown sequence and the voltage on the FADE pin does not
change the power-up sequence. Upon a power-up condition, the TPA6021A4 begins in the lowest gain setting
and steps up 2 dB every 2 clock cycles until the final value is reached as determined by the dc voltage applied to
the VOLUME pin.
Figure 22. Shutdown Sequence in the
Figure 23. Shutdown Sequence in the
Fade-on Mode
Fade-off Mode
14
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