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參數(shù)資料
| 型號(hào)： | TPA28F800CV-T80 |
| 廠商： | Intel Corp. |
| 英文描述： | 2-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 2兆位SmartVoltage啟動(dòng)塊閃存系列 |
| 文件頁數(shù)： | 44/55頁 |
| 文件大?。?/td> | 638K |
| 代理商： | TPA28F800CV-T80 |
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2-MBIT SmartVoltage BOOT BLOCK FAMILY
E
44
SEE NEW DESIGN RECOMMENDATIONS
4.9.1
APPLYING V
CC
VOLTAGES
When applying V
CC
voltage to the device, a delay
may be required before initiating device operation,
depending on the V
CC
ramp rate. If V
CC
ramps
slower than 1V/100 μs (0.01 V/μs) then no delay is
required. If V
CC
ramps faster than 1V/100 μs (0.01
V/μs), then a delay of 2 μs is required before
initiating device operation. RP# = GND is
recommended during power-up to protect against
spurious write signals when V
CC
is between V
LKO
and V
CCMIN
.
V
CC
Ramp Rate
Required Timing
≤
1V/100
μ
s
No delay required.
> 1V/100
μ
s
A delay time of 2
μ
s is required before any device operation is initiated, including read
operations, command writes, program operations, and erase operations. This delay
is
measured beginning from the time V
CC
reaches V
CCMIN
( 3.0 V for 3.3
±
0.3 V operation;
and 4.5 V for 5 V operation).
NOTES:
1.
2.
These requirements must be strictly followed to guarantee all other read and write specifications.
To switch between 3.3 V and 5 V operation, the system should first transition V
from the existing voltage range to GND,
and then to the new voltage.
Any time the V
CC
supply drops below V
CCMIN
, the chip may be reset, aborting any operations
pending or in progress.
These guidelines must be followed for any V
CC
transition from GND.
3.
4.10
T
A
= 25 °C, f = 1 MHz
Capacitance
Symbol
Parameter
Note
Typ
Max
Unit
Conditions
C
IN
Input Capacitance
1
6
8
pF
V
IN
= 0V
C
OUT
Output Capacitance
1
10
12
pF
V
OUT
= 0V
NOTE:
1. Sampled, not 100% tested.
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