• 參數(shù)資料
    型號: TPA28F200CV-T60
    廠商: Intel Corp.
    英文描述: USB 2.0 Cables; Connector Type A:USB Type A Male; Connector Type B:USB Type B Male; Cable Length:10ft; Approval Bodies:UR, CSA; Contact Material:Platinum; Wire Size (AWG):28-24
    中文描述: 2兆位SmartVoltage啟動塊閃存系列
    文件頁數(shù): 13/55頁
    文件大?。?/td> 638K
    代理商: TPA28F200CV-T60
    E
    2.0
    2-MBIT SmartVoltage BOOT BLOCK FAMILY
    13
    SEE NEW DESIGN RECOMMENDATIONS
    PRODUCT DESCRIPTION
    2.1
    Memory Blocking Organization
    This product family features an asymmetrically-
    blocked architecture providing system memory
    integration. Each erase block can be erased
    independently of the others up to 100,000 times for
    commercial temperature or up to 10,000 times for
    extended temperature. The block sizes have been
    chosen to optimize their functionality for common
    applications of nonvolatile storage. The combination
    of block sizes in the boot block architecture allow
    the integration of several memories into a single
    chip. For the address locations of the blocks, see
    the memory maps in Figures
    4 and 5.
    2.1.1
    ONE 16-KB BOOT BLOCK
    The boot block is intended to replace a dedicated
    boot PROM in a microprocessor or microcontroller-
    based system.
    The 16-Kbyte (16,384 bytes) boot
    block is located at either the top (denoted by -T
    suffix) or the bottom (-B suffix) of the address map
    to accommodate different microprocessor protocols
    for boot code location. This boot block features
    hardware controllable write-protection to protect the
    crucial microprocessor boot code from accidental
    modification. The protection of the boot block is
    controlled using a combination of the V
    PP
    , RP#, and
    WP# pins, as is detailed in Section
    3.4.
    2.1.2
    TWO 8-KB PARAMETER BLOCKS
    The boot block architecture includes parameter
    blocks to facilitate storage of frequently updated
    small parameters that would normally require an
    EEPROM. By using software techniques, the byte-
    rewrite functionality of EEPROMs can be emulated.
    These techniques are detailed in Intel’s application
    note AP-604, Using Intel’s Boot Block Flash
    Memory Parameter Blocks to Replace EEPROM
    .
    Each boot block component contains two parameter
    blocks of 8 Kbytes (8,192 bytes) each. The
    parameter blocks are not write-protectable.
    2.1.3
    ONE 96-KB + ONE 128-KB MAIN
    BLOCK
    After the allocation of address space to the boot
    and parameter blocks, the remainder is divided into
    main blocks for data or code storage. Each 2-Mbit
    device contains one 96-Kbyte (98,304 byte) block
    and one 128-Kbyte (131,072 byte) block. See the
    memory maps for each device for more information.
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    相關代理商/技術參數(shù)
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