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參數(shù)資料
| 型號： | TPA2054D4YZKT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 0.94 W, 2 CHANNEL, AUDIO AMPLIFIER, BGA25 |
| 封裝： | 2.61 X 2.61 MM, GREEN, DSBGA-25 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 949K |
| 代理商： | TPA2054D4YZKT |
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SINGLE-BYTE WRITE
MULTI-BYTE WRITE AND INCREMENTAL MULTI-BYTE WRITER
SINGLE-BYTE READ
SLOS607 – APRIL 2009 ..................................................................................................................................................................................................... www.ti.com
As shown in Figure 44, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit must be set to 0. After receiving the correct I2C
device address and the read/write bit, the TPA2054D4 responds with an acknowledge bit. Next, the master
transmits the register byte corresponding to the TPA2054D4 internal memory address being accessed. After
receiving the register byte, the TPA2054D4 again responds with an acknowledge bit. Finally, the master device
transmits a stop condition to complete the single-byte data write transfer.
Figure 44. Single-Byte Write Transfer
A multiple-byte data write transfer is identical to a single-byte data write transfer with the exception that multiple
data bytes are transmitted by the master device to the TPA2054D4 as shown in Figure 45. After receiving each
data byte, the TPA2054D4 responds with an acknowledge bit.
Figure 45. Multiple-Byte Write Transfer
As shown in Figure 46, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte of the internal memory
address to be read. As a result, the read/write bit is set to a 0.
After receiving the TPA2054D4 address and the read/write bit, the TPA2054D4 responds with an acknowledge
bit. The master then sends the internal memory address byte, after which the TPA2054D4 issues an
acknowledge bit. The master device transmits another start condition followed by the TPA2054D4 address and
the read/write bit again. This time, the read/write bit is set to 1, indicating a read transfer. Next, the TPA2054D4
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not-acknowledge followed by a stop condition to complete the single-byte data read transfer.
Figure 46. Single-Byte Read Transfer
14
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TPA2054D4
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