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參數(shù)資料
| 型號： | TP82510 |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 異步串行控制器 |
| 文件頁數(shù)： | 3/14頁 |
| 文件大小： | 76K |
| 代理商： | TP82510 |
IA82510
ASYNCHRONOUS SERIAL CONTROLLER
Functional Overview
Transmitter
The Transmit function consists of a 4
×
11 bit FIFO, and a Transmit Engine. The 4
×
11 FIFO is
configurable as any depth between one and four words inclusive. The transmit engine is
responsible for reading the data out of the FIFO and placing it in the proper order on the TXD pin.
The transmit engine is highly configurable to be compatible with numerous formats, including
16450 and 8250 modes of communication. Transmit Communication parameters that can be
programmed include:
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
RTS and CTS modes
See the Register Description for more details.
Data Sheet
As of Production Ver. 01
Copyright
2001
innov
ASIC
The End of Obsolescence
ENG211001219-01
www.innovasic.com
Customer Support:
Page 3 of 14
1-888-824-4184
Receiver
The Receiver function consists of a 4
×
11 configurable FIFO and a Receive Engine. The receive
engine is responsible for sampling the data on the RXD input pin, formatting the data, and placing
the data in the FIFO. The receive engine is highly configurable with parameters that include:
Parity modes
Stop Bits
Character Length
FIFO Depth
Clocking Options
Address Matching Options
Control Character Detection
RTS and CTS modes
See the Register Description for more details.
Bus Interface
The Bus Interface is a simple interface that allows a micro-processor or micro-controller to read
and write the IA82510 Registers. It consists of the following I/O lines:
A0, A1, A2 :
3 Bit Address
D0-D7 :
8 Bit Data
RDn:
Active Low Read Enable
WRn:
Active Low Write Enable
CSn:
Active Low Chip Select
INT:
Interrupt Output
RESET:
Chip Reset
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