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參數(shù)資料
| 型號： | TP5510 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Full Duplex Analog Front End for Consumer Applications |
| 中文描述： | 全雙工模擬前端的消費應用 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 197K |
| 代理商： | TP5510 |
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
V
CC
to GNDA
V
BB
to GNDA
Voltage at any Analog Input
or Output
7V
b
7V
V
CC
a
0.3V to V
BB
b
0.3V
Voltage at any Digital Input or
Output
V
CC
a
0.3V to GNDA
b
0.3V
b
25
§
C to
a
125
§
C
b
65
§
C to
a
150
§
C
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
300
§
C
2000V
ESD (Human Body Model)
Latch-Up Immunity
e
100 mA on any Pin
Electrical Characteristics
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
CC
e
5.0V
g
5%, V
BB
e b
5.0V
g
5%; T
A
e
0
§
C to 70
§
C by correlation with 100% electrical testing at T
A
e
25
§
C. All other limits
are assured by correlation with other production tests and/or product design and characterization. All signals referenced to
GNDA. Typicals specified at V
CC
e
5.0V, V
BB
e b
5.0V, T
A
e
25
§
C.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INTERFACE
V
IL
V
IH
V
OL
Input Low Voltage
0.6
V
Input High Voltage
2.2
V
Output Low Voltage
D
E
, I
L
e
3.2 mA
SIG
D
, I
L
e
1.0 mA
TS
E
, I
L
e
3.2 mA, Open Drain
D
E
, I
H
eb
3.2 mA
SIG
D
, I
H
eb
1.0 mA
GNDA
s
V
IN
s
V
IL
, All Digital Inputs
V
IH
s
V
IN
s
V
CC
D
E
, GNDA
s
V
O
s
V
CC
0.4
0.4
0.4
V
V
V
V
OH
Output High Voltage
2.4
2.4
V
V
I
IL
I
IH
I
OZ
Input Low Current
b
10
b
10
b
10
10
m
A
Input High Current
10
m
A
Output Current in High Impedance
State (TRI-STATE)
10
m
A
ANALOG INTERFACE WITH ENCODE INPUT AMPLIFIER (ALL DEVICES)
I
I
EA
R
I
EA
R
O
EA
R
L
EA
C
L
EA
V
O
EA
A
V
EA
F
U
EA
V
OS
EA
V
CM
EA
CMRREA
Input Leakage Current
b
2.5V
s
V
s
a
2.5V, VF
E
I
a
or VF
E
I
b
b
2.5V
s
V
s
a
2.5V, VF
E
I
a
or VF
E
I
b
Closed Loop, Unity Gain
b
200
10
200
nA
Input Resistance
M
X
Output Resistance
1
3
X
Load Resistance
GS
E
GS
E
GS
E
, R
L
t
10 k
X
VF
E
I
a
to GS
E
10
k
X
Load Capacitance
50
pF
Output Dynamic Range
b
2.8
5000
2.8
V
Voltage Gain
V/V
Unity Gain Bandwidth
1
2
MHz
Offset Voltage
b
20
b
2.5
60
20
mV
Common-Mode Voltage
CMRREA
l
60 dB
2.5
V
Common-Mode Rejection Ratio
DC Test
dB
PSRREA
Power Supply Rejection Ratio
DC Test
60
dB
ANALOG INTERFACE WITH DECODE FILTER (ALL DEVICES)
R
O
DF
R
L
DF
C
L
DF
VOS
D
O
POWER DISSIPATION (ALL DEVICES)
Output Resistance
Pin VF
D
O
VF
D
O
e
g
2.5V
1
3
X
Load Resistance
600
X
Load Capacitance
500
pF
Output DC Offset Voltage
b
200
200
mV
I
CC
0
I
BB
0
I
CC
1
I
BB
1
Power-Down Current
No Load (Note)
0.5
3
mA
Power-Down Current
No Load (Note)
0.05
1
mA
Power-Up Active Current
No Load
6.0
12
mA
Power-Up Active Current
No Load
6.0
12
mA
Note:
I
CC
0 and I
BB
0 are measured after first achieving a power-up state.
http://www.national.com
5
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