參數(shù)資料
型號(hào)： TP3465
廠商： National Semiconductor Corporation
英文描述： TP3465 MICROWIRETM Interface Device (MID)
中文描述： TP3465 MICROWIRETM接口設(shè)備（MID）
文件頁(yè)數(shù)： 7/17頁(yè)
文件大?。?/td> 295K
代理商： TP3465
Functional Description
(Continued)
Example 1: Communicating with 8-bit peripheralDdevice 0:
The
mwm0
bit must be set to 0. Write the MICROWIRE
data in to the FMBD0 address. The 8-bit data is then shifted
out after the trailing edge of the write pulse. The Chip Select
(CS0) is automatically activated (LOW) and deactivated
(HIGH) by hardware before and after the data transfer (see
timing diagrams). The 8-bit STATUS from the peripheral is
read from the FMBD0 byte location.
Example 2: Communicating with 16-bit peripheralDdevice
0:
The
mwm0
bit must be set to 1. Write the LOW byte of
MICROWIRE data into the SMB data register and then write
the HIGH byte in to the FMBD0 address. The 16-bit data is
then shifted out after the trailing edge of the write strobe
signal for this FMBD0 address. The Chip Select 0 (CS0) pin
is automatically activated (LOW) and deactivated (HIGH) by
hardware before and after the data transfer (see timing dia-
grams). The 16-bit STATUS from the peripheral is read from
the FMBD0 (HIGH data byte) and the SMB (LOW data byte)
locations.
FMBD1DFirst MICROWIRE Byte Dev1: R/W Register
Same function as FMBD0 except this refers to Device 1 and
Chip Select 1 (CS1).
FMBD2DFirst MICROWIRE Byte Dev2: R/W Register
Same function as FMBD0 except this refers to Device 2 and
Chip Select 2 (CS2).
FMBD3DFirst MICROWIRE Byte Dev3: R/W Register
Same function as FMBD0 except this refers to Device 3 and
Chip Select 3 (CS3).
FMBD4DFirst MICROWIRE Byte Dev4: R/W Register
Same function as FMBD0 except this refers to Device 4 and
Chip Select 4 (CS4).
FMBD5DFirst MICROWIRE Byte Dev5: R/W Register
Same function as FMBD0 except this refers to Device 5 and
Chip Select 5 (CS5).
FMBD6DFirst MICROWIRE Byte Dev6: R/W Register
Same function as FMBD0 except this refers to Device 6 and
Chip Select 6 (CS6).
FMBD7DFirst MICROWIRE Byte Dev7: R/W Register
Same function as FMBD0 except this refers to Device 7 and
Chip Select 7 (CS7).
MICROWIRE Master/Slave Modes
MICROWIRE MASTER MODE
The primary application for MID is as a master of MICRO-
WIRE bus (
ms
bit in CKR register set to 0), and as such it
provides the SK clock out to the peripheral devices. It trans-
mits data on the SO pin and receives data on the SI pin. The
CS0–7 pins are used as chip select pins for the peripherals
and have a predefined relationship with the SK clock output.
Writing to the FMB pin causes the most significant bit to be
output immediately to the SO pin, and the
uwdone
bit is
automatically reset to 0. Upon completion of transfer of ei-
ther 8 bits (
mwm7
e
0) or 16 bits (
mwm7
e
1), the
uwdone
bit is set to 1. The SO pin is then set to the TRI-
STATE
é
condition. Note that when using the FMB and SMB
registers, the communication mode is determined by the pa-
rameters for channel 7 (mwm7 and skp7).
MICROWIRE SLAVE MODE
The MID can be set to work in MICROWIRE Slave mode by
setting the
ms
bit to 1. The MICROWIRE clock from the
master is connected to the CKIN pin of this MID device. The
SK output is ignored. Normally the SO pin is in TRI-STATE
condition and, while the uwdone bit is 1, any CKIN clock
inputs are ignored. Writing to the FMB register causes the
most significant bit to be output immediately to the SO pin
and the
uwdone
bit is reset to 0 by hardware. The SK clock
input is then enabled to clock data into SI and out of SO.
After receiving SK clock pulses; either 8 (
mwm7
e
0) or 16
bits (
mwm7
e
1), the
uwdone
bit is set to 1 by hardware.
The SO pin is then set to TRI-STATE condition. Note that
when using the FMB and SMB registers, the communication
mode is determined by the parameters of channel 7 (mwm7
and skp7).
FMBD0–7 addresses are not used in the slave mode. The
CS register, however, can be used as a general I/O port
control register.
See applications section for an example of the Slave opera-
tion (Figure 6).
MICROWIRE BUS FORMATS
MID supports devices which implement either of the two
MICROWIRE bus formats; a 3-pin format and a 4-pin format.
Figure 3 shows a MID connected to devices supporting
each of these formats.
The standard 4-pin format consists of the CCLK clock pin,
CO and CI as the data out and data in pins, and CS to select
the MICROWIRE peripheral. ISDN transceivers and other
intelligent peripherals also have an INTerrupt signal from
the peripheral to the local microprocessor. NSC MICRO-
WIRE devices with this 4-pin format include ISDN transceiv-
ers, COMBO II, LCD display drivers and EEPROMs.
There are, however, some MICROWIRE peripherals (e.g.,
TP3071 COMBO II, and some EEPROMs) which support a
3-pin bus format because of package pin limitations. The
format consists of the CCLK clock signal, a bi-directional
data signal CO/CI, and a CS chip select signal. The direc-
tion of the data transferred on the CO/CI pin is determined
by a protocol between the Master and the Slave of the MI-
CROWIRE bus. For example, the TP3071 implements a
two-byte protocol. The first byte into the TP3071 indicates a
Read or a Write operation and thus defines the direction of
the next byte to the device.
Software Driver Procedures
This section describes the steps for software driver routines
to communicate with different MICROWIRE devices (8-bit,
16-bit, or more) and those supporting the 3-pin or 4-pin
MICROWIRE bus formats.
INITIALIZATION
1. Write to PD (Pin Definition) register to set the desired chip
select control pins (CS0–7) as outputs. (All CS pins are
set to inputs on chip RESET.)
2. Write to SKP (SK polarity), to select the polarity of the SK
clock for each of the MICROWIRE devices connected to
CS0–7 pins.
3. Write to MWM (MICROWIRE Mode) register to select
whether 8- or 16-bit devices are attached to the CS0–7
pins. Devices needing more than 16-bits may still be con-
figured as 8-bit mode (if multiple of 8) or 16-bit mode (if
multiple of 16 bits).
7
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