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參數(shù)資料
| 型號： | TP3401 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | DASL Digital Adapter for Subscriber Loops |
| 中文描述： | DASL適配器數(shù)字用戶環(huán)路 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 249K |
| 代理商： | TP3401 |
Connection Diagrams
TP3401 DASL
TL/H/9264–2
Order Number TP3401J
See NS Package Number J20A
TP3402 DASL
TL/H/9264–15
Order Number TP3402J
See NS Package Number J20A
TP3403 Package Information
TL/H/9264–16
Order Number TP3403V
See NS Package Number V28A
Pin Descriptions
Name
Description
GND
Negative power supply pin, normally 0V. All
analog and digital signals are referred to this
pin.
V
CC
Positive power supply input, which must be
a
5V
g
5%.
The 2.048 MHz Master Clock input, which
(TP3401 only) requires a CMOS logic level clock input from
a stable source. Must be synchronous with
BCLK.
MCLK
MCLK/XTAL
(TP3402/3403 put, which requires either a crystal to be con-
only)
nected between this pin and XTAL2 or a
CMOS logic level clock from a stable source,
which must be synchronous with BCLK.
This pin is the 2.048 MHz Master Clock in-
XTAL2
(TP3402 and
TP3403 only)
This pin is the output side of the oscillator
amplifier.
MBS/FS
C
(TP3401 and
TP3403 only) to synchronize Transmit bursts from a num-
ber of devices at the Master end only. The 4
kHz should be nominally a square wave sig-
nal. If not used leave this pin open. In Slave
mode, this pin is a short Frame Sync output,
suitable for driving another DASL in Master
Mode to provide a regenerator (i.e. range-ex-
tender) capability.
In Master Mode, this pin is the Master Burst
Sync input, which may be clocked at 4 kHz
BCLK
Bit Clock logic signal which determines the
data shift rate for B channel data on the digi-
tal interface side of the device. In Master
mode this pin is an input which may be any
multiple
of
8
kHz
2.048 MHz, but must be synchronous with
MCLK. In Slave mode this pin is an output at
2.048 MHz.
from
256
kHz
to
FS
a
In Master mode only, this pin is the Transmit
Frame Sync pulse input, requiring a positive
edge to indicate the start of the active chan-
nel time for transmit B channel data into B
x
;
FS
a
must be synchronous with BCLK and
MCLK. In Slave mode only, this pin is a digi-
Name
Description
tal output pulse which indicates the 8-bit pe-
riods of the B1 channel data transfer at both
B
x
and B
r
.
In Master mode only, this pin is the Receive
Frame Sync pulse input, requiring a positive
edge to indicate the start of the active chan-
nel time of the device for receive B channel
data out from B
r
; FS
b
must be synchronous
with BCLK and MCLK. In Slave mode only,
this pin is a digital output pulse which indi-
cates the 8-bit periods of the B2 channel
data transfer at both B
x
and B
r
.
Digital input for B1 and B2 channel data to
be transmitted to the line; must be synchro-
nous with BCLK.
FS
b
B
x
B
r
Digital output for B1 and B2 channel data
received from the line.
TS
r
/LSD
In Master mode only, this pin is an open-
drain output which is normally high imped-
ance but pulls low during both B channel ac-
tive receive time slots. In Slave mode only,
this pin is an output which is normally high
impedance and pulls low when a valid line
signal is received.
D
x
Digital input for D channel data to be trans-
mitted to the line; must be synchronous with
DCLK.
D
r
Digital output for D channel data received
from the line.
DCLK/DEN
In Master mode this pin is an input for the
16 kHz serial shift clock for D channel data
on D
x
and D
r
, which should be synchronous
with BCLK. It may also be re-configured via
the Control Register to act as an enable in-
put for clocking the D channel interface syn-
chronized to BCLK. In Slave mode this is a
16 kHz clock output for D channel data.
*
Crystal specifications: 2.048 MHz parallel resonant, R
S
s
100
X
with a
20 pF load. Crystal tolerance should be
g
75 ppm for aging and tempera-
ture.
2
相關PDF資料 |
PDF描述 |
|---|---|
| TP3402 | DASL Digital Adapter for Subscriber Loops |
| TP3403 | DASL Digital Adapter for Subscriber Loops |
| TP3404 | Quad Digital Adapter for Subscriber Loops (QDASL) |
| TP3404V | Quad Digital Adapter for Subscriber Loops (QDASL) |
| TP3406 | DASL Digital Adapter for Subscriber Loops |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TP3401S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TRANSISTOR | BJT | NPN | 200MA I(C) | FO-58VAR |
| TP3402 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:DASL Digital Adapter for Subscriber Loops |
| TP3402J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN Line Interface |
| TP3403 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:DASL Digital Adapter for Subscriber Loops |
| TP3403V | 功能描述:通信集成電路 - 若干 Digital Adptr for Subscriber Loops RoHS:否 制造商:Maxim Integrated 類型:Transport Devices 封裝 / 箱體:TECSBGA-256 數(shù)據速率:100 Mbps 電源電壓-最大:1.89 V, 3.465 V 電源電壓-最小:1.71 V, 3.135 V 電源電流:50 mA, 225 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Tube |
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