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參數(shù)資料
| 型號(hào)： | TP3155V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 數(shù)字傳輸電路 |
| 英文描述： | TP3155 Time Slot Assignment Circuit |
| 中文描述： | DATACOM, TIME SLOT ASSIGNER, PQCC20 |
| 封裝： | PLASTIC, LCC-20 |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 208K |
| 代理商： | TP3155V |
Functional Description
OPERATING MODES
The TP3155 control interface requires an 8-bit serial control
word which is compatible with the TP3020/TP3021 and
2910/2911 CODECs. Two bits, X and R, define which of the
two groups of frame sync outputs, FS
X
0 to FS
X
3 or FS
R
0 to
FS
R
3, is affected by the control word, and a 6-bit assign-
ment field specifies the selected time slot, from 0 to 31. A
frame sync output is active-high for one time slot, which is
always 8 cycles of BCLK. A frame may consist of any num-
ber of time slots up to 32. If a timeslot is assigned which is
beyond the number of time slots in a frame, the FS
X
or FS
R
output to which it was assigned will remain inactive.
Two modes of operation are available. Mode 1 is for sys-
tems requiring different time slot assignments for the trans-
mit and receive direction of each channel. Mode 1 is select-
ed by leaving pin 9 (MODE) open-circuit or connecting it to
V
CC
. In this case, Pin 13 is the RSYNC input which defines
the start of each receive frame, and the four outputs,
FS
R
0–FS
R
3, are assigned with respect to RSYNC. The
XSYNC input defines the start of each transmit frame and
outputs FS
X
0–FS
X
3 are assigned with respect to XSYNC.
XSYNC may have any phase relationship with RSYNC. In-
puts CH0 and CH1 select the channel, from 0 to 3 (see
Table Ia).
Mode 2 provides the option of assigning all 8 frame sync
outputs with respect to the XSYNC input. Mode 2 is select-
ed by connecting pin 9 (MODE) to GND. This makes the
TP3155 TSAC useful for either an 8-channel undirectional
controller or for systems in which the transmit and receive
directions of each channel are always assigned to the same
time slot as the other, i.e., the FS
X
and FS
R
inputs on the
COMBO CODEC/Filter are hard-wired together. In this
case, logical selection of the channel to be assigned is
made via inputs CH0, CH1 and CH2 (see Table Ib).
POWER-UP INITIALIZATION
During power-up, all frame sync outputs, FS
X
0–FS
X
3 and
FS
R
0–FS
R
3, are inhibited and held low. No outputs will go
active until a valid time slot assignment is made.
LOADING CONTROL DATA
During the loading of control data, the binary code for the
selected channel must be set on inputs CH0 and CH1 (and
CH2 in mode 2), see Tables Ia and Ib.
Control data is clocked into the D
C
input on the falling
edges of CLK
C
while CS is low.
A new time slot assignment is transferred to the selected
assignment register on the high going transition of CS. The
new assignment is re-synchronized to the system clock
such that the new FS output pulses will start at the next
complete valid time slot after the rising edge of CS.
TIME SLOT COUNTER OPERATION
At the start of TS0 of each transmit frame, defined by the
first falling edge of BCLK after XSYNC goes high, the trans-
mit time slot counter is reset to 000000 and begins to incre-
ment once every 8 cycles of BCLK. Each count is compared
with the 4 transmit assignment registers and, on finding a
match, a frame sync pulse is generated at that FS
X
output.
Similarly, the first falling edge of BCLK after RSYNC goes
high defines the start of receive TS0, and outputs
FS
R
0–FS
R
3 are generated with respect to TS0 when the
receive time slot counter matches the appropriate receive
assignment register.
TS
X
OUTPUT
In mode 1 (separate transmit and receive assignments), this
output pulls low whenever any FS
X
output pulse is being
generated. In mode 2, this output pulls low whenever any
FS
X
or FS
R
output is being generated. At all other times it is
open-circuit, allowing the TS
X
outputs of a number of
TSACS to be wire-ANDed together with a common pull-up
resistor. This signal can be used to control the TRI-STATE
é
enable input of a line driver to buffer the transmit PCM bus
from the CODEC/Filters to the backplane.
TABLE Ia. Control Mode 1
(TP3020/TP3021 Compatible)
X
R
T5
T4
T3
T2
T1
T0
X is the first bit clocked into the D
C
input.
Control Data Format
T5
T4
T3
T2
T1
T0
Time Slot
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
2
:
0
0
1
1
1
X
1
1
X
1
1
X
1
1
X
0
1
X
30
31
(Note 1)
CH1
CH0
Channel Selected
0
0
1
1
0
1
0
1
Assign to FS
x
0 and/or FS
R
0
Assign to FS
x
1 and/or FS
R
1
Assign to FS
x
2 and/or FS
R
2
Assign to FS
x
3 and/or FS
R
3
X
R
Action
0
0
1
1
0
1
0
1
Assign time slot to both selected FS
X
and FS
R
Assign time slot to selected FS
X
only
Assign time slot to selected FS
R
only
Disable both selected FS
X
and FS
R
TABLE Ib. Control Mode 2
CH2
CH1
CH0
Channel Selected
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Assign to FS
X
0
Assign to FS
X
1
Assign to FS
X
2
Assign to FS
X
3
Assign to FS
R
0
Assign to FS
R
1
Assign to FS
R
2
Assign to FS
R
3
X
R
Action
0
0
1
1
0
1
Assign time slot to selected output
0
(
1
Disable selected output
Note 1:
When T5
e
1, then the appropriate FS
X
or FS
R
output is inactive.
5
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