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參數(shù)資料
| 型號(hào)： | TP3155 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | TP3155 Time Slot Assignment Circuit |
| 中文描述： | TP3155時(shí)隙分配電路 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | TP3155 |
Definitions and Timing Conventions
DEFINITIONS
V
IH
V
IH
is the d.c. input level above which
an input level is guaranteed to appear
as a logical one. This parameter is to
be measured by performing a function-
al test at reduced clock speeds and
nominal timing, (i.e. not minimum setup
and hold times or output strobes), with
the high level of all driving signals set
to V
IH
and maximum supply voltages
applied to the device.
V
IL
V
IL
is the d.c. input level below which
an input level is guaranteed to appear
as a logical zero to the device. This pa-
rameter is measured in the same man-
ner as V
IH
but with all driving signal low
levels set to V
IL
and minimum supply
voltages applied to the device.
V
OH
V
OH
is the minimum d.c. output level to
which an output placed in a logical one
state will converge when loaded at the
maximum specified load current.
V
OL
V
OL
is the maximum d.c. output level to
which an output placed in a logical zero
state will converge when loaded at the
maximum specified load current.
Threshold Region
The threshold region is the range of in-
put voltages between V
IL
and V
IH
.
A signal is Valid if it is in one of the valid
logic states, (i.e. above V
IH
or below
V
IL
). In timing specifications, a signal is
deemed valid at the instant it enters a
valid state.
Valid Signal
Invalid Signal
A signal is Invalid if it is not in a valid
logic state, i.e. when it is in the thresh-
old region between V
IL
and V
IH
. In tim-
ing specifications, a signal is deemed
Invalid at the instant it enters the
threshold region.
TIMING CONVENTIONS
For the purposes of this timing specification the following
conventions apply:
Input Signals
All input signals may be characterized
as: V
L
e
0.4V, V
H
e
2.4V, t
R
k
10 ns,
t
F
k
10ns.
The period of clock signal is designated
as t
Pxx
where xx represents the mne-
monic of the clock signal being speci-
fied.
Period
Rise Time
Rise times are designated as t
Ryy
,
where yy represents a mnemonic of the
signal whose rise time is being speci-
fied. t
Ryy
is measured from V
IL
to V
IH
.
Fall times are designated as t
Fyy
,
where yy represents a mnemonic of the
signal whose fall time is being speci-
fied. t
Fyy
is measured from V
IH
to V
IL
.
The high pulse width is designated as
t
WzzH
, where zz represents the mne-
monic of the input or output signal
whose pulse width is being specified.
High pulse widths are measured from
V
IH
to V
IH
.
The low pulse width is designated as
t
WzzL
, where zz represents the mne-
monic of the input or output signal
whose pulse width is being specified.
Low pulse widths are measured from
V
IL
to V
IL
.
Setup times are designated as t
Swwxx
,
where ww represents the mnemonic of
the input signal whose setup time is be-
ing specified relative to a clock or
strobe input represented by mnemonic
xx. Setup times are measured from the
ww Valid to xx Invalid.
Fall Time
Pulse Width High
Pulse Width Low
Setup Time
Hold Time
Hold times are designated as t
Hxxww
,
where ww represents the mnemonic of
the input signal whose hold time is be-
ing specified relative to a clock or
strobe input represented by mnemonic
xx. Hold times are measured from xx
Valid to ww Invalid.
Delay Time
Delay
t
Dxxyy
[
H
L
]
, where xx represents the
mnemonic of the input reference signal
and yy represents the mnemonic of the
output signal whose timing is being
specified relative to xx. The mnemonic
may optionally be terminated by an H
or L to specify the high going or low
going transition of the output signal.
Maximum delay times are measured
from xx Valid to yy Valid. Minimum de-
lay times are measured from xx Valid to
yy Invalid. This parameter is tested un-
der the load conditions specified in the
Conditions column of the Timing Speci-
fications section of this data sheet.
times
are
designated
as
6
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