參數(shù)資料
型號： TP3071N
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 編解碼器
英文描述： COMBO II Programmable PCM CODEC/Filter
中文描述： A/MU-LAW, PROGRAMMABLE CODEC, PDIP20
封裝： PLASTIC, DIP-20
文件頁數(shù)： 12/26頁
文件大?。?/td> 401K
代理商： TP3071N
Electrical Characteristics
(Continued)
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5V
±
5%, V
= 5V
±
5%; T
= 0C to
+70C (40C to +85C for TP3070-X) by correlation with 100% electrical testing at T
= 25C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
specified at V
CC
= +5V, V
BB
= 5V, T
A
= 25C.
Symbol
Parameter
Conditions
POWER DISSIPATION
I
BB
1
Power Up Current
As Above
40C to +85C (TP3070-X)
I
CC
2
Power Down Current
Power Amp Enabled
40C to +85C (TP3070-X)
I
BB
2
Power Down Current
Power Amp Enabled
40C to +85C (TP3070-X)
Min
Typ
Max
Units
8.0
11.0
13.0
3.0
4.0
3.0
4.0
mA
mA
mA
mA
mA
mA
2.0
2.0
Note 9:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 10:
See definitions and timing conventions section.
Timing Specifications
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5V
±
5%; V
= 5V
±
5%; T
= 0C to
+70C (40C to +85C for TP3070-X) by correlation with 100% electrical testing at T
= 25C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
specified at V
= +5V, V
= 5V, T
= 25C.
All timing parameters are measured at V
= 2.0V and V
= 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
MASTER CLOCK TIMING
f
MCLK
Frequency of MCLK
Selection of Frequency is
Programmable (See Table 5)
Min
Typ
Max
Units
512
1536
1544
2048
4096
kHz
kHz
kHz
kHz
kHz
ns
ns
ns
ns
ns
t
WMH
t
WML
t
RM
t
FM
t
HBM
Period of MCLK High
Period of MCLK Low
Rise Time of MCLK
Fall Time of MCLK
HOLD Time, BCLK LOW
to MCLK HIGH
Period of F
SX
or F
SR
Low
PCM INTERFACE TIMING
f
BCLK
Frequency of BCLK
Measured from V
IH
to V
IH
(Note 11)
Measured from V
IL
to V
IL
(Note 11)
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
TP3070 Only
80
80
30
30
50
t
WFL
Measured from V
IL
to V
IL
1
MCLK Period
May Vary from 64 kHz to 4096 kHz
in 8 kHz Increments
Measured from V
IH
to V
IH
Measured from V
IL
to V
IL
Measured from V
IL
to V
IH
Measured from V
IH
to V
IL
64
4096
kHz
t
WBH
t
WBL
t
RB
t
FB
t
HBF
Period of BCLK High
Period of BCLK Low
Rise Time of BCLK
Fall Time of BCLK
Hold Time, BCLK Low
to FS
X/R
High or Low
Setup Time, FS
X/R
High to BCLK Low
Delay Time, BCLK High
to Data Valid
80
80
ns
ns
ns
ns
ns
30
30
30
t
SFB
30
ns
t
DBD
Load = 100 pF Plus 2 LSTTL Loads
40C to +85C (TP3070-X)
80
90
ns
ns
www.national.com
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