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參數(shù)資料
| 型號(hào)： | TP3071J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | COMBO II Programmable PCM CODEC/Filter |
| 中文描述： | A/MU-LAW, PROGRAMMABLE CODEC, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 401K |
| 代理商： | TP3071J |
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Timing Specifications
(Continued)
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5V
±
5%; V
= 5V
±
5%; T
= 0C to
+70C (40C to +85C for TP3070-X) by correlation with 100% electrical testing at T
= 25C. All other limits are assured by
correlation with other production tests and/or product design and characterization. All signals referenced to GND. Typicals
specified at V
= +5V, V
= 5V, T
= 25C.
All timing parameters are measured at V
= 2.0V and V
= 0.7V.
See Definitions and Timing Conventions section for test methods information.
Symbol
Parameter
Conditions
PCM INTERFACE TIMING
t
DBZ
Delay Time, BCLK Low to D
X
0/1
D
X
0/1 Disabled is measured at V
OL
or V
OH
according to Figure 4 or
Figure 5
D
X
0/1 disabled if 8th BCLK
Low, or BCLK High to D
X
0/1
Disabled if FS
X
High
40C to +85C (TP3070-X)
t
DBT
Delay Time, BCLK High to TS
X
Low if FS
X
High, or FS
X
High to
TS
X
Low if BCLK High (Non
Delayed Mode); BCLK High to
TS
X
Low (Delayed Data Mode)
t
ZBT
TRI-STATE Time, BCLK Low to
TS
X
High if FS
X
Low, FS
X
Low
to TS
X
High if 8th BCLK Low, or
BCLK High to TS
X
High if FS
X
High
t
DFD
Delay Time, FS
X/R
Load = 100 pF Plus 2 LSTTL Loads,
High to Data Valid
Applies if FS
X/R
Rises Later than
BCLK Rising Edge in Non-Delayed
Data Mode Only
40C to +85C (TP3070-X)
t
SDB
Setup Time, D
R
0/1
Valid to BCLK Low
t
HBD
Hold Time, BCLK
Low to D
R
0/1 Invalid
40C to +85C (TP3070-X)
SERIAL CONTROL PORT TIMING
f
CCLK
Frequency of CCLK
t
WCH
Period of CCLK High
Measured from V
IH
to V
IH
t
WCL
Period of CCLK Low
Measured from V
IL
to V
IL
t
RC
Rise Time of CCLK
Measured from V
IL
to V
IH
t
FC
Fall Time of CCLK
Measured from V
IH
to V
IL
t
HCS
Hold Time, CCLK Low
CCLK1
to CS Low
t
HSC
Hold Time, CCLK
CCLK 8
Low to CS High
t
SSC
Setup Time, CS
Transition to CCLK Low
t
SSCO
Setup Time, CS
Transition to CCLK High
t
SDC
Setup Time, CI (CI/O)
Data In to CCLK Low
t
HCD
Hold Time, CCLK
Low to CI/O Invalid
t
DCD
Delay Time, CCLK High
Load = 100 pF plus 2 LSTTL Loads
to CI/O Data Out Valid
40C to +85C (TP3070-X)
Min
Typ
Max
Units
Disabled if FS
X
Low, FS
X
Low to
15
80
ns
15
100
60
ns
ns
Load = 100 pF Plus 2 LSTTL Loads
15
60
ns
80
ns
90
ns
ns
30
15
15
ns
ns
2048
kHz
ns
ns
ns
ns
ns
160
160
50
50
10
100
ns
60
ns
50
ns
50
ns
50
ns
80
100
ns
ns
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| TP3070V | COMBO II Programmable PCM CODEC/Filter |
| TP3071 | COMBO II Programmable PCM CODEC/Filter |
| TP3071N | COMBO II Programmable PCM CODEC/Filter |
| TP3070J | COMBO II Programmable PCM CODEC/Filter |
| TP3070V-X | COMBO II Programmable PCM CODEC/Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3071N | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3071NG | 制造商:National Semiconductor 功能描述:Audio Codec 1ADC / 1DAC 20-Pin PDIP Rail |
| TP3071N-G | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3071N-G/NOPB | 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3072V-X | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law/u-Law CODEC |
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