參數(shù)資料
型號(hào)： TP3070J
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 編解碼器
英文描述： COMBO II Programmable PCM CODEC/Filter
中文描述： A/MU-LAW, PROGRAMMABLE CODEC, CDIP28
封裝： CERAMIC, DIP-28
文件頁(yè)數(shù)： 4/26頁(yè)
文件大?。?/td> 401K
代理商： TP3070J
Functional Description
(Continued)
POWER-DOWN STATE
Following a period of activity in the powered-up state the
power-down state may be re-entered by writing any of the
control instructions into the serial control port with the “P” bit
set to “1” as indicated in Table 1 It is recommended that the
chip be powered down before writing any additional instruc-
tions. In the power-down state, all non-essential circuitry is
de-activated and the D
0 (and D
X
1) outputs are in the high
impedance TRI-STATE condition.
The coefficients stored in the Hybrid Balance circuit and the
Gain Control registers, the data in the LDR and ILR, and all
control bits remain unchanged in the power-down state un-
less changed by writing new data via the serial control port,
which remains active. The outputs of the Interface Latches
also remain active, maintaining the ability to monitor and
control the SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VF
I, is a high impedance sum-
ming input which is used as the differencing point for the in-
ternal hybrid balance cancellation signal. No external com-
ponents are necessary to set the gain. Following this circuit
is a programmable gain/attenuation amplifier which is con-
trolled by the contents of the Transmit Gain Register (see
Programmable Functions section). An active pre-filter then
precedes the 3rd order high-pass and 5th order low-pass
switched capacitor filters. The A/D converter has a com-
pressing characteristic according to the standard CCITTA or
μ255 coding laws, which must be selected by a control in-
struction during initialization (see Table 1and Table 2).Apre-
cision on-chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage arising in the
gain-set amplifier, the filters or the comparator is canceled by
an internal auto-zero circuit.
Each encode cycle begins immediately following the as-
signed Transmit time-slot. The total signal delay referenced
to the start of the time-slot is approximately 165 μs (due to
the Transmit Filter) plus 125 μs (due to encoding delay),
which totals 290 μs. Data is shifted out on D
0 or D
1 during
the selected time slot on eight rising edges of BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive PCM Regis-
ter via the D
0 or D
1 pin during the selected time-slot on
the 8 falling edges of BCLK. The Decoder consists of an ex-
panding DAC with either A or μ255 law decoding character-
istic, which is selected by the same control instruction used
to select the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor filter with
integral Sin x/x correction for the 8 kHz sample and hold. A
programmable gain amplifier, which must be set by writing to
the Receive Gain Register, is included, and finally a Power
Amplifier capable of driving a 300
load to
±
3.5V, a 600
load to
±
3.8V or a 15 k
load to
±
4.0V at peak overload.
A decode cycle begins immediately after the assigned re-
ceive time-slot, and 10 μs later the Decoder DAC output is
updated. The total signal delay is 10 μs plus 120 μs (filter de-
lay) plus 62.5 μs (
1
2
frame) which gives approximately 190
μs.
PCM INTERFACE
The FS
and FS
frame sync inputs determine the begin-
ning of the 8-bit transmit and receive time-slots respectively.
They may have any duration from a single cycle of BCLK
HIGH to one MCLK period LOW. Two different relationships
may be established between the frame sync inputs and the
actual time-slots on the PCM busses by setting bit 3 in the
Control Register (see Table 2). Non-delayed data mode is
similar to long-frame timing on the TP3050/60 series of de-
vices (COMBO); time-slots begin nominally coincident with
the rising edge of the appropriate FS input. The alternative is
to use Delayed Data mode, which is similar to short-frame
sync timing on COMBO, in which each FS input must be high
at least a half-cycle of BCLK earlier than the time-slot. The
Time-Slot Assignment circuit on the device can only be used
with Delayed Data timing.
When using Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate FS input.
The actual transmit and receive time-slots are then deter-
mined by the internal Time-Slot Assignment counters.
Transmit and Receive frames and time-slots may be skewed
from each other by any number of BCLK cycles. During each
assigned Transmit time-slot, the selected D
0/1 output shifts
data out from the PCM register on the rising edges of BCLK.
TS
0 (or TS
1 as appropriate) also pulls low for the first 7
1
2
bit times of the time-slot to control the TRI-STATE Enable of
a backplane line-driver. Serial PCM data is shifted into the
selected D
0/1 input during each assigned Receive time-slot
on the falling edges of BCLK. D
0 or D
1 and D
R
0 or D
R
1
are selectable on the TP3070 only, see Section 6.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TP3070V 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter
TP3070V-G 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP3070V-G/63 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP3070V-G/63SN 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TP3070V-G/NOPB 功能描述:接口—CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
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