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參數(shù)資料
| 型號(hào)： | TP3069WM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編解碼器 |
| 英文描述： | ``Enhanced' Serial Interface CMOS CODEC/Filter COMBO |
| 中文描述： | A-LAW, PCM CODEC, PDSO20 |
| 封裝： | 0.300 INCH, PLASTIC, SOP-20 |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 275K |
| 代理商： | TP3069WM |
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Functional Description
(Continued)
The FS
X
frame sync pulse controls the sampling of the filter
output, and then the successive-approximation encoding cy-
cle begins. The 8-bit code is then loaded into a buffer and
shifted out through D
X
at the next FS
X
pulse. The total en-
coding delay will be approximately 165
m
s (due to the trans-
mit filter) plus 125
m
s (due to encoding delay), which totals
290
m
s. Any offset voltage due to the filters or comparator is
cancelled by sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding DAC which
drives a fifth order switched-capacitor low pass filter
clocked at 256 kHz. The decoder is A-law and the 5th order
low pass filter corrects for the sin x/x attenuation due to the
8 kHz sample/hold. The filter is then followed by a 2nd or-
der RC active post-filter with its output at VF
R
O. The receive
section is unity-gain, but gain can be added by using the
power amplifiers. Upon the occurrence of FS
R
, the data at
the D
R
input is clocked in on the falling edge of the next
eight BCLK
R
(BCLK
X
) periods. At the end of the decoder
time slot, the decoding cycle begins, and 10
m
s later the
decoder DAC output is updated. The total decoder delay is
E
10
m
s (decoder update) plus 110
m
s (filter delay) plus
62.5
m
s (
(/2
frame), which gives approximately 180
m
s.
RECEIVE POWER AMPLIFIERS
Two inverting mode power amplifiers are provided for direct-
ly driving a matched line interface transformer. The gain of
the first power amplifier can be adjusted to boost the
g
2.5V
peak output signal from the receive filter up to
g
3.3V peak
into an unbalanced 300
X
load, or
g
4.0V into an unbal-
anced 15 k
X
load. The second power amplifier is internally
connected in unity-gain inverting mode to give 6 dB of signal
gain for balanced loads.
Maximum power transfer to a 600
X
subscriber line termina-
tion is obtained by differentially driving a balanced trans-
former with a
S
2:1 turns ratio, as shown inFigure 4. A total
peak power of 15.6 dBm can be delivered to the load plus
termination.
D
0
1
V
IN
e b
Full-Scale
0
0
ENCODING FORMAT AT D
X
OUTPUT
TP3069
A-Law
(Includes Even Bit Inversion)
V
IN
e a
Full-Scale
V
IN
e
0V
1
1
0
1
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TP3070-X | |
| TP3070 | COMBO II Programmable PCM CODEC/Filter(COMBO II可編程PCM信號(hào)編解碼器/濾波器) |
| TP3071AN | COMBO II Programmable PCM CODEC/Filter |
| TP3071J | COMBO II Programmable PCM CODEC/Filter |
| TP3070V | COMBO II Programmable PCM CODEC/Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3069WMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP-306A-CF-H1141-L1000 | 制造商:TURCK Inc 功能描述:TP-306A-CF-H1141-L1000 |
| TP307 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
| TP3070 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:COMBO II Programmable PCM CODEC/Filter |
| TP3070AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law/u-Law CODEC |
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