Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC <" />
參數(shù)資料
型號(hào)： TP3067V-X
廠商： National Semiconductor
文件頁(yè)數(shù)： 19/20頁(yè)
文件大小： 0K
描述： IC INTERFACE ENHANCED SER 20PLCC
標(biāo)準(zhǔn)包裝： 40
類(lèi)型： PCM 編解碼器/濾波器
數(shù)據(jù)接口： 串行
分辨率（位）： 8 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 無(wú)
電壓 - 電源，模擬： ±5V
電壓 - 電源，數(shù)字： ±5V
工作溫度： -25°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 20-PLCC
包裝： 帶卷 (TR)
其它名稱(chēng)： *TP3067V-X
Timing Specifications
Unless otherwise noted limits printed in BOLD characters are guaranteed for VCC ea50V g5% VBB eb50V g5% TA e
0 Cto70 C by correlation with 100% electrical testing at TA e 25 C All other limits are assured by correlation with other
production tests andor product design and characterization All signals are referenced to GNDA Typicals specified at VCC e
a
50V VBB eb50V TA e 25 C All timing parameters are measured at VOH e 20V and VOL e 07V
See Definitions and Timing Conventions section for test methods information
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1tPM
Frequency of Master Clock
1536
MHz
1544
MHz
MCLKX and MCLKR
2048
MHz
tRM
Rise Time of Master Clock
MCLKX and MCLKR
50
ns
tFM
Fall Time of Master Clock
MCLKX and MCLKR
50
ns
tPB
Period Bit of Clock
485
488
15725
ns
tRB
Rise Time of Bit Clock
BCLKX and BCLKR
50
ns
tFB
Fall Time of Bit Clock
BCLKX and BCLKR
50
ns
tWMH
Width of Master Clock High
MCLKX and MCLKR
160
ns
tWML
Width of Master Clock Low
MCLKX and MCLKR
160
ns
tSBFM
Set-Up Time from BCLKX High
100
ns
to MCLKX Falling Edge
tSFFM
Set-Up Time from FSX High
Long Frame Only
100
ns
to MCLKX Falling Edge
tWBH
Width of Bit Clock High
160
ns
tWBL
Width of Bit Clock Low
160
ns
tHBFL
Holding Time from Bit Clock
Long Frame Only
0
ns
Low to Frame Sync
tHBFS
Holding Time from Bit Clock
Short Frame Only
0
ns
High to Frame Sync
tSFB
Set-Up Time for Frame Sync
Long Frame Only
80
ns
to Bit Clock Low
tDBD
Delay Time from BCLKX High
Loade150 pF plus 2 LSTTL Loads
0
180
ns
to Data Valid
tDBTS
Delay Time to TSX Low
Loade150 pF plus 2 LSTTL Loads
140
ns
tDZC
Delay Time from BCLKX Low to
50
165
ns
Data Output Disabled
tDZF
Delay Time to Valid Data from
CLe0 pF to 150 pF
20
165
ns
FSX or BCLKX Whichever
Comes Later
tSDB
Set-Up Time from DR Valid to
50
ns
BCLKRX Low
tHBD
Hold Time from BCLKRX Low to
50
ns
DR Invalid
tSF
Set-Up Time from FSXR to
Short Frame Sync Pulse (1 Bit Clock
50
ns
BCLKXR Low
Period Long)
tHF
Hold Time from BCLKXR Low
Short Frame Sync Pulse (1 Bit Clock
100
ns
to FSXR Low
Period Long)
tHBFI
Hold Time from 3rd Period of
Long Frame Sync Pulse (from 3 to 8 Bit
100
ns
Bit Clock Low to Frame Sync
Clock Periods Long)
(FSX or FSR)
tWFL
Minimum Width of the Frame
64k Bits Operating Mode
160
ns
Sync Pulse (Low Level)
7
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