- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10933 > TP3057WMX/NOPB (National Semiconductor)IC INTERFACE ENHANCED SER 16SOIC PDF資料下載
參數(shù)資料
| 型號： | TP3057WMX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 0K |
| 描述： | IC INTERFACE ENHANCED SER 16SOIC |
| 標準包裝： | 1,000 |
| 類型： | PCM 編解碼器/濾波器 |
| 數(shù)據(jù)接口： | 串行 |
| ADC / DAC 數(shù)量： | 1 / 2 |
| 三角積分調(diào)變： | 無 |
| 電壓 - 電源，模擬： | ±5V |
| 電壓 - 電源，數(shù)字： | ±5V |
| 工作溫度： | -25°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | TP3057WMX |
Block Diagram
FIGURE 1
TLH5510 – 2
Pin Description
Symbol
Function
VBB
Negative power supply pin
VBB eb5V g5%
GNDA
Analog ground All signals are referenced
to this pin
VFRO
Analog output of the receive power ampli-
fier
VCC
Positive power supply pin
VCC ea5V g5%
FSR
Receive frame sync pulse which enables
BCLKR to shift PCM data into DR FSR is
an 8 kHz pulse train See
Figures 2 and 3
for timing details
DR
Receive data input PCM data is shifted
into DR following the FSR leading edge
BCLKR CLKSEL The bit clock which shifts data into DR af-
ter the FSR leading edge May vary from
64 kHz to 2048 MHz Alternatively may
be a logic input which selects either
1536 MHz1544 MHz or 2048 MHz for
master clock in synchronous mode and
BCLKX is used for both transmit and re-
ceive directions (see Table I)
MCLKR PDN
Receive
master
clock
Must
be
1536 MHz 1544 MHz or 2048 MHz
May be asynchronous with MCLKX but
Symbol
Function
should be synchronous with MCLKX for best per-
formance When MCLKR is connected continu-
ously low MCLKX is selected for all internal tim-
ing When MCLKR is connected continuously
high the device is powered down
MCLKX
Transmit master clock Must be 1536 MHz
1544 MHz or 2048 MHz May be asynchronous
with MCLKR Best performance is realized from
synchronous operation
FSX
Transmit frame sync pulse input which enables
BCLKX to shift out the PCM data on DX FSX is
an 8 kHz pulse train see
Figures 2 and 3 for
timing details
BCLKX
The bit clock which shifts out the PCM data on
DX May vary from 64 kHz to 2048 MHz but
must be synchronous with MCLKX
DX
The TRI-STATE
PCM data output which is en-
abled by FSX
TSX
Open drain output which pulses low during the
encoder time slot
GSX
Analog output of the transmit input amplifier
Used to externally set gain
VFXIb
Inverting input of the transmit input amplifier
VFXIa
Non-inverting input of the transmit input amplifi-
er
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-2NH-CU | CONVERTER MOD DC/DC 52V 200W |
| VE-2NF-CU | CONVERTER MOD DC/DC 72V 200W |
| MCF5280CVM80 | IC MPU 32BIT COLDF 256-MAPBGA |
| MC68HC16Z1CEH20 | IC MPU 16BIT 20MHZ 132-PQFP |
| MCF5470VR200 | IC MPU 32BIT COLDF 388-PBGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TP3057-X | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Extended Temperature Serial Interface CODEC/Filter COMBO Family |
| TP3058 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:MICROPROCESSOR COMPATIBLE COMBO-R |
| TP3058J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3059 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:MICROPROCESSOR COMPATIBLE COMBO-R |
| TP3059J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:MICROPROCESSOR COMPATIBLE COMBO-R |
發(fā)布緊急采購，3分鐘左右您將得到回復。