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參數資料
| 型號： | TP3056BDW |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| 中文描述： | 整體式串行接口的PCM編解碼器和過濾器 |
| 文件頁數： | 14/19頁 |
| 文件大?。?/td> | 287K |
| 代理商： | TP3056BDW |
TP3056B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SLWS072A – MAY 1998 – REVISED AUGUST 1998
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
system reliability and design considerations (continued)
device power-up sequence
Latch-up also can occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1.
Ensure that no signals are applied to the device before the power-up sequence is complete.
2.
Connect GND.
3.
Apply V
BB
(most negative voltage).
Apply V
CC
(most positive voltage).
Force a power down condition in the device.
4.
5.
6.
Connect clocks.
7.
Release the power down condition.
8.
Apply FS synchronization pulses.
9.
Apply the signal inputs.
When powering down the device, this procedure should be followed in the reverse order.
internal sequencing
Power-on reset circuitry initializes the TP3056B device when power is first applied, placing it in the power-down
mode. The DX and VFRO outputs go into the high-impedance state and all nonessential circuitry is disabled.
A low level applied to the PDN terminal powers up the device and activates all internal circuits. The 3-state PCM
data output, DX, remains in the high-impedance state until the arrival of the second FSX pulse.
general operation
A 2.048-MHz clock signal applied to MCLK serves as the master clock for both the receive and the transmit
directions. BCLK must have a bit clock signal applied to it, which then serves as the bit clock for both the receive
and the transmit directions. BCLK can be in the range from 64 kHz to 2.048 MHz, but must be synchronous with
MCLK.
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled DX output on the rising edge of BCLK. After eight bit-clock periods, the 3-state DX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched in via DR on the falling edge of BCLK.
FSX and FSR must be synchronous with MCLK.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| TP3056BDWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3056BN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數量:2 DAC 數量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3056J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PARALLEL INTERFACE CODEC/FILTER COMBO |
| TP3056V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law CODEC |
| TP3057 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Enhanced Serial Interface CODEC/Filter COMBO Family |
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