參數(shù)資料
型號(hào): TP3054WM-X
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 編解碼器
英文描述: Extended Temperature Serial Interface CODEC/Filter COMBO Family
中文描述: MU-LAW, PCM CODEC, PDSO16
封裝: DSO-16
文件頁(yè)數(shù): 2/16頁(yè)
文件大?。?/td> 671K
代理商: TP3054WM-X
Pin Descriptions
Symbol
Function
V
BB
Negative power supply pin.
V
BB
= 5V
±
5%.
Analog ground. All signals are
referenced to this pin.
Analog output of the receive power
amplifier.
Positive power supply pin.
V
CC
= +5V
±
5%.
Receive frame sync pulse which
enables BCLK
R
to shift PCM data into
D
R
. FS
R
is an 8 kHz pulse train. See
Figure 2
and
Figure 3
for timing details.
Receive data input. PCM data is shifted
into D
R
following the FS
R
leading edge.
GNDA
VF
R
O
V
CC
FS
R
D
R
Symbol
Function
BCLK
R
/CLKSEL The bit clock which shifts data into D
R
after the FS
R
leading edge. May vary
from 64 kHz to 2.048 MHz.
Alternatively, may be a logic input
which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in
synchronous mode and BCLK
X
is used
for both transmit and receive directions
(see
Table 1
).
MCLK
R
/PDN
Receive master clock. Must be 1.536
MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
X
, but should
be synchronous with MCLK
X
for best
performance. When MCLK
R
is
connected continuously low, MCLK
X
is
selected for all internal timing. When
MCLK
R
is connected continuously high,
the device is powered down.
Block Diagram
00867402
FIGURE 1.
T
www.national.com
2
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TP3054-X 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Extended Temperature Serial Interface CODEC/Filter COMBO Family