參數(shù)資料
型號(hào): TP3054N
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 編解碼器
英文描述: Enhanced Serial Interface CODEC/Filter COMBO Family
中文描述: MU-LAW, PCM CODEC, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 5/16頁
文件大?。?/td> 671K
代理商: TP3054N
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
to GNDA
V
BB
to GNDA
Voltage at any Analog Input
or Output
7V
7V
V
CC
+0.3V to V
BB
0.3V
Voltage at any Digital Input or
Output
Operating Temperature Range
Storage Temperature Range
Lead Temperature
(Soldering, 10 sec.)
V
CC
+0.3V to GNDA0.3V
55C to + 125C
65C to +150C
300C
Electrical Characteristics
Unless otherwise noted, limits printed in
BOLD
characters are guaranteed for V
= +5.0V
±
5%, V
= 5.0V
±
5%; T
=
40C to +85C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. All signals referenced to GNDA. Typicals specified at V
CC
=
+5.0V, V
BB
= 5.0V, T
A
= 25C.
Symbol
Parameter
DIGITAL INTERFACE
V
IL
Input Low Voltage
V
IH
Input High Voltage
V
OL
Output Low Voltage
D
X
, I
L
=3.2 mA
SIG
R
, I
L
=1.0 mA
TS
X
, I
L
=3.2 mA, Open Drain
V
OH
Output High Voltage
D
X
, I
H
=3.2 mA
SIG
R
, I
H
=1.0 mA
I
IL
Input Low Current
GNDA
V
IN
V
IL
, All Digital Inputs
I
IH
Input High Current
V
IH
V
IN
V
CC
I
OZ
Output Current in High Impedance
D
X
, GNDA
V
O
V
CC
State (TRI-STATE)
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (ALL DEVICES)
I
I
XA
Input Leakage Current
2.5V
V
+2.5V, VF
X
I
+
or VF
X
I
R
I
XA
Input Resistance
2.5V
V
+2.5V, VF
X
I
+
or VF
X
I
R
O
XA
Output Resistance
Closed Loop, Unity Gain
R
L
XA
Load Resistance
GS
X
C
L
XA
Load Capacitance
GS
X
V
O
XA
Output Dynamic Range
GS
X
, R
L
10 k
A
V
XA
Voltage Gain
VF
X
I
+
to GS
X
F
U
XA
Unity Gain Bandwidth
V
OS
XA
Offset Voltage
V
CM
XA
Common-Mode Voltage
CMRRXA
Common-Mode Rejection Ratio
DC Test
PSRRXA
Power Supply Rejection Ratio
DC Test
ANALOG INTERFACE WITH RECEIVE FILTER (ALL DEVICES)
R
O
RF
Output Resistance
Pin VF
R
O
R
L
RF
Load Resistance
VF
R
O=
±
2.5V
C
L
RF
Load Capacitance
VOS
R
O
Output DC Offset Voltage
POWER DISSIPATION (ALL DEVICES)
I
CC
0
Power-Down Current
No Load (Note 2)
I
BB
0
Power-Down Current
No Load (Note 2)
I
CC
1
Power-Up (Active) Current
No Load( –40C to 85C)
I
BB
1
Power-Up (Active) Current
No Load ( –40C to 85C)
Conditions
Min
Typ
Max
Units
0.6
V
V
V
V
V
V
V
μA
μA
μA
2.2
0.4
0.4
0.4
2.4
2.4
10
10
10
10
10
10
200
10
200
nA
M
k
pF
V
V/V
MHz
mV
V
dB
dB
1
3
10
50
2.8
2.8
5000
1
20
2.5
60
60
2
20
2.5
CMRRXA
>
60 dB
1
3
pF
mV
600
500
200
200
0.65
0.01
5.0
5.0
2.0
0.33
11.0
11.0
mA
mA
mA
mA
Note 1:
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2:
I
CC0
and I
BB0
are measured after first achieving a power-up state.
T
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