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參數(shù)資料
| 型號： | TP3054 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | “Enhanced” Serial Interface CMOS CODEC/Filter(加強型串行接口CMOS編解碼器/濾波器) |
| 中文描述： | “增強”串行接口的CMOS編解碼器/過濾器（加強型串行接口的CMOS編解碼器/濾波器） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 250K |
| 代理商： | TP3054 |
Block Diagram
FIGURE 1
TL/H/5510–2
Pin Description
Symbol
Function
V
BB
Negative power supply pin.
V
BB
e b
5V
g
5%.
Analog ground. All signals are referenced
to this pin.
GNDA
VF
R
O
Analog output of the receive power ampli-
fier.
V
CC
Positive power supply pin.
V
CC
e a
5V
g
5%.
Receive frame sync pulse which enables
BCLK
R
to shift PCM data into D
R
. FS
R
is
an 8 kHz pulse train. SeeFigures 2 and3
for timing details.
FS
R
D
R
Receive data input. PCM data is shifted
into D
R
following the FS
R
leading edge.
BCLK
R
/CLKSEL The bit clock which shifts data into D
R
af-
ter the FS
R
leading edge. May vary from
64 kHz to 2.048 MHz. Alternatively, may
be a logic input which selects either
1.536 MHz/1.544 MHz or 2.048 MHz for
master clock in synchronous mode and
BCLK
X
is used for both transmit and re-
ceive directions (see Table I).
MCLK
R
/PDN
Receive
1.536 MHz, 1.544 MHz or 2.048 MHz.
May be asynchronous with MCLK
X
, but
master
clock.
Must
be
Symbol
Function
should be synchronous with MCLK
X
for best per-
formance. When MCLK
R
is connected continu-
ously low, MCLK
X
is selected for all internal tim-
ing. When MCLK
R
is connected continuously
high, the device is powered down.
MCLK
X
Transmit master clock. Must be 1.536 MHz,
1.544 MHz or 2.048 MHz. May be asynchronous
with MCLK
R
. Best performance is realized from
synchronous operation.
FS
X
Transmit frame sync pulse input which enables
BCLK
X
to shift out the PCM data on D
X
. FS
X
is
an 8 kHz pulse train, see Figures 2 and 3 for
timing details.
BCLK
X
The bit clock which shifts out the PCM data on
D
X
. May vary from 64 kHz to 2.048 MHz, but
must be synchronous with MCLK
X
.
The TRI-STATE
é
PCM data output which is en-
abled by FS
X
.
Open drain output which pulses low during the
encoder time slot.
D
X
TS
X
GS
X
Analog output of the transmit input amplifier.
Used to externally set gain.
VF
X
I
b
VF
X
I
a
Inverting input of the transmit input amplifier.
Non-inverting input of the transmit input amplifi-
er.
2
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PDF描述 |
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| TP3056BDWR | PCM CODEC|SINGLE|CMOS|SOP|16PIN|PLASTIC |
| TP3056B | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3056BDW | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3056BN | MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3098 | TRANSISTOR | BJT | NPN | 200MA I(C) | RFMOD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TP3054A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER |
| TP3054ADW | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3054ADWR | 功能描述:接口—CODEC Mono Serial Intfc PCM Codec/Filter RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TP3054AJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:u-Law CODEC |
| TP3054AN | 功能描述:接口—CODEC PCM CODEC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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