參數(shù)資料
型號: TP28F010-90
廠商: INTEL CORP
元件分類: DRAM
英文描述: 28F010 1024K (128K X 8) CMOS FLASH MEMORY
中文描述: 128K X 8 FLASH 12V PROM, 90 ns, PDIP32
封裝: 0.620 X 1.640 INCH, PLASTIC, DIP-32
文件頁數(shù): 25/33頁
文件大?。?/td> 895K
代理商: TP28F010-90
E
28F010
25
Output
0.8
Test Points
Input
2.0
2.0
0.8
2.4
0.45
0207_06
AC test inputs are driven at V
(2.4 V
) for a Logic
“1”
and V
(0.45 V
) for a Logic “0”. Input timing begins at
V
(2.0 V
) and V
(0.8 V
). Output timing ends at V
IH
and V
IL
. Input rise and fall times (10% to 90%)
<
10 ns.
Figure 6. Testing Input/Output Waveform
(1)
NOTE:
1.
Testing characteristics for 28F010-90, 28F010-120, and
28F010-150.
Device
Under Test
Out
R
L
= 3.3 k
1N914
1.3V
C
L
= 100 pF
0207_07
C
L
Includes Jig Capacitance
Figure 7. AC Testing Load Circuit
4.8
AC Characteristics
—Read-Only Operations—Commercial and Extended
Temperature Products
Versions
28F010-90
(1)
28F010-120
(1)
28F010-150
(1)
Symbol
Characteristic
Notes
Min
Max
Min
Max
Min
Max
Unit
t
AVAV
/t
RC
Read Cycle Time
90
120
150
ns
t
ELQV
/t
CE
CE# Access Time
90
120
150
ns
t
AVQV
/t
ACC
Address Access Time
90
120
150
ns
t
GLQV
/t
OE
OE# Access Time
35
50
55
ns
t
ELQX
/t
LZ
CE# to Low Z
2, 3
0
0
0
ns
t
EHQZ
Chip Disable to Output in
High Z
2
45
55
55
ns
t
GLQX
/t
OLZ
OE# to Output in Low Z
2, 3
0
0
0
ns
t
GHQZ
/t
DF
Output Disable to Output in
High Z
2
30
30
35
ns
t
OH
Output Hold from Address,
CE#, or OE# Change
2, 4
0
0
0
ns
t
WHGL
Write Recovery Time before
Read
6
6
6
μs
NOTES:
1.
2.
3.
4.
See AC Input/Output Waveformand AC Testing Load Circuitfor testing characteristics.
Sampled, not 100% tested.
Guaranteed by design.
Whichever occurs first.
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