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參數(shù)資料
| 型號： | TP28F010-150 |
| 廠商： | INTEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 28F010 1024K (128K X 8) CMOS FLASH MEMORY |
| 中文描述： | 128K X 8 FLASH 12V PROM, 150 ns, PDIP32 |
| 封裝： | 0.620 X 1.640 INCH, PLASTIC, DIP-32 |
| 文件頁數(shù)： | 14/33頁 |
| 文件大?。?/td> | 895K |
| 代理商： | TP28F010-150 |
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28F010
E
14
Start
Programming
(4)
Apply V
PPH
(1)
PLSCNT = 0
Write Set-Up
Program Cmd
Write Program
Verify Cmd
Read Data
from Device
Write Read Cmd
Verify
Data
Inc
PLSCNT
=25
Last
Address
Programming
Completed
Program
Error
Write Program
Cmd (A/D)
Time Out 10 μs
Apply V
PPL
(1)
Apply V
PPL
(1)
Time Out 6 μs
Increment
Address
N
Bus
Operation
Command
Comments
Initialize Pulse-Count
Write
Set-Up
Program
Data = 40H
Write
Program
Valid Address/Data
Standby
Duration of Program
Operation (t
WHWH1
)
Write
Program
Verify
(2)
Data = C0H; Stops
Program Operations
(3)
Stand-by
t
WHGL
Read
Read Byte to Verify
Programming
Standby
Wait for V
PP
Ramp to
V
PPH
(1)
Standby
Compare Data Output to
Data Expected
Standby
Wait for V
PP
Ramp to V
PPL
(1)
Write
Read
Data = 00H, Resets the
Register for Read
Operations
Y
N
Y
Y
N
0207_04
NOTES:
1.
2.
See DC Characteristicsfor the value of V
PPH
and V
PPL
.
Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the
register is written with the Read command.
Refer to Principles of Operation
CAUTION:
The algorithm
must be followed
to ensure proper and reliable operation of the device.
3.
4.
Figure 4. 28F010 Quick-Pulse Programming Algorithm
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