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參數(shù)資料
| 型號： | TP13057BN |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | CAPACITOR 18000UF 35V ELECT TSUP |
| 中文描述： | 整體式串行接口的PCM編解碼器和過濾器 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 249K |
| 代理商： | TP13057BN |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCMCODEC AND FILTER
SCTS042A – MAY 1990 – REVISED JULY 1996
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
operating characteristics, over operating free-air temperature range, V
CC
= 5 V
±
5%,
V
BB
= –5 V
±
5%, GND at 0 V, V
I
= 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity
gain, noninverting (unless otherwise noted)
timing requirements
PARAMETER
TEST CONDITIONS
MIN
TYP
1.536
1.544
2.048
MAX
UNIT
fclock(M)
Frequency of master clock
MCLKX and
MCLKR
Depends on the device used and
BCLKX/CLKSEL
MHz
fclock(B)
tw1
tw2
Frequency of bit clock, transmit
Pulse duration, MCLKX and MCLKR high
Pulse duration, MCLKX and MCLKR low
BCLKX
64
160
160
2.048
kHz
ns
ns
tr1
Rise time of master clock
MCLKX and
MCLKR
MCLKX and
MCLKR
Measured from 20% to 80%
50
ns
tf1
Fall time of master clock
Measured from 20% to 80%
50
ns
tr2
tf2
Rise time of bit clock, transmit
Fall time of bit clock, transmit
Setup time, BCLKX high (and FSX in long-frame sync
mode) before MCLKX
↓
Pulse duration, BCLKX and BCLKR high
Pulse duration, BCLKX and BCLKR low
Hold time, frame sync low after bit clock low
(long frame only)
Hold time, BCLKX high after frame sync
↑
(short frame only)
Setup time, frame sync high before bit clock
↓
(long frame only)
BCLKX
BCLKX
Measured from 20% to 80%
Measured from 20% to 80%
First bit clock after the leading edge
of FSX
50
50
ns
ns
tsu1
100
ns
tw3
tw4
VIH = 2.2 V
VIL = 0.6 V
160
160
ns
ns
th1
0
ns
th2
0
ns
tsu2
80
ns
td1
td2
Delay time, BCLKX high to data valid
Delay time, BCLKX high to TSX low
Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled
Load = 150 pF plus 2 LSTTL loads
Load = 150 pF plus 2 LSTTL loads
0
140
140
ns
ns
td3
50
165
ns
td4
Delay time, FSX or BCLKX high to data valid
(long frame only)
Setup time, DR valid before BCLKR
↓
Hold time, DR valid after BCLKR or BCLKX
↓
Setup time, FSR or FSX high before BCLKR or
BCLKR
↓
CL = 0 pF to 150 pF
20
165
ns
tsu3
th3
50
50
ns
ns
tsu4
Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)
50
ns
th4
Hold time, FSX or FSR high after BCLKX or BCLKR
↓
Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)
100
ns
th5
Hold time, frame sync high after bit clock
↓
Long-frame sync pulse (from 3 to
8 bit clock periods long)
100
ns
tw5
Minimum pulse duration of the frame sync pulse
(low level)
All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25
°
C.
Nominal input value for an LSTTL lead is 18 k
.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
64 kbps operating mode
160
ns
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