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參數(shù)資料
| 型號： | TP11362 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | CONNECTOR |
| 中文描述： | 連接器 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大小： | 442K |
| 代理商： | TP11362 |
Absolute Maximum Ratings
(Note *NO
TGT: FNXref NS0465*)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V
CC
to GND
Voltage at Any Digital
Inputs or Outputs
7V
GND 0.3V to V
CC
+ 0.3V
Storage Temperature Range
Lead Temperature
(Soldering, 10 sec)
Latch-up Immunity on any Pin
θ
JA
(28-pin PLCC)
θ
JA
(24-pin DIP)
45C to +125C
300C
±
75 mA
79C/W
49C/W
DC Electrical Characteristics
Unless otherwise noted, limits printed in
bold
characters are guaranteed forV
= 5.0V
±
5%, GND1 = GND2 = 0V, T
=
40C to +85C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at V
CC
= +5V, T
A
= 25C.
Symbol
Parameter
Conditions
I
CC0
Supply Current
CLK = 8.0 MHz, RSTB = Low
(Power Down Mode)
I
CC1
Supply Current
CLK = 8.0 MHz, RSTB = High
(Power Up Mode)
P
D
Power Dissipation
V
IL
Input Low Voltage
ASCK, PSCK, CE, TRB,
V
IH
Input High Voltage
CLK, RSTB
V
IL
Input Low Voltage
PCM1, RSI, TSI, QSEL0,
V
IH
Input High Voltage
QSEL1, INIT, EN
V
OL
Output Low Voltage
I
L
= 4 mA
V
OH
Output High Voltage
I
L
= 4 mA
I
L
= 0.4 mA; V
CC
= 4.75V
I
IL
Input Low Current
I
IH
Input High Current
Test Inputs TST0, TST1, TST2 (Note 4)
I
OZ
Output Current in High
Impedance State
C
I
Input Capacitance
C
O
Output Capacitance
C
L
Capacitive Load
Min
Typ
Max
1.8
Units
mA
7
9
mA
35
mW
V
V
V
V
V
V
V
μA
μA
μA
μA
0.8
2.4
0.7
2.0
0.4
2.4
V
CC
0.8
10
GND
<
V
IN
<
V
IL
, All Signal Inputs
V
IH
<
V
IN
<
V
CC
, All Signal Inputs
10
150
10
GND
<
V
O
<
V
CC
, TSO and RS0
10
10
10
100
pF
pF
pF
Note 4:
Test inputs have internal pull-down resistor.
Timing Specifications
Unless otherwise noted, limits printed in
bold
characters are guaranteed for V
= 5.0V
±
5%, GND1 = GND2 = 0V, T
=
40C to +85C by correlation with 100% electrical testing at T
= 25C. All other limits are assured by correlation with other
production tests and/or product design and characterization. Typical values are specified at V
CC
= +5V, T
A
= 25C.
Symbol
Parameter
Conditions
f
CLK
CLK Frequency (Note 5)
Assuming 50% Duty Cycle
t
CLK
CLK Duty-Cycle
Min
7.9
40%
Typ
8.0
50%
Max
16
60%
Units
MHz
CLK
Period
ns
t
R
Rise Time (CLK, CE,
ASCK, PSCK)
Fall Time (CLK, CE,
ASCK, PSCK)
CE Period
10
t
F
10
ns
t
CEP
Encode or Decode
Initialization
Disable
123
45
9
CLK
Cycles
t
CEL
CE Pulse Width, Low
4
CLK
Cycles
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