20.5. VDD Monitor (VDDMON0) High Threshold Setting <" />
參數(shù)資料
型號: TOOLSTICK530TPP
廠商: Silicon Laboratories Inc
文件頁數(shù): 127/220頁
文件大?。?/td> 0K
描述: ADAPTER PROG TOOLSTICK F530TPP
標(biāo)準(zhǔn)包裝: 1
系列: ToolStick
類型: 微控制器編程器
適用于相關(guān)產(chǎn)品: C8051F530/531/533/534/536/537-IT
所含物品: 2 個板和 USB 連接線纜
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336-1499-5-ND - IC 8051 MCU 4K FLASH 20QFN
336-1498-5-ND - IC 8051 MCU 4K FLASH 20TSSOP
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其它名稱: 336-1457
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C8051F52x/F53x
212
Rev. 1.4
20.5. VDD Monitor (VDDMON0) High Threshold Setting
The calibration behavior of the internal voltage regulator (REG0) and its impact on VDD monitor
(VDDMON0) high threshold setting differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
The following note applies to Revision A and Revision B devices: The output of the internal voltage reg-
ulator (REG0) is calibrated by the MCU immediately after any reset event. The output of the un-calibrated
internal regulator could be below the high threshold setting (VRST-HIGH) of the VDD Monitor (VDDMON0). If
this is the case and the VDD Monitor is set to the high threshold setting and if the MCU receives a non-
power on reset, the MCU will remain in reset until a power-on reset (POR) occurs (i.e. VDD Monitor will
keep the device in reset). A POR will force the VDD Monitor to the low threshold setting which is guaran-
teed to be below the un-calibrated output of the internal regulator. The device will then exit reset and
resume normal operation. It is for this reason Silicon Labs strongly recommends that the VDD Monitor is
always left in the low threshold setting (i.e., default value upon POR).
When programming the Flash in-system, the VDD Monitor (VDDMON0) must be set to the high threshold
setting. For the highest system reliability, the time the VDD Monitor is set to the high threshold setting
should be minimized (e.g., setting the VDD Monitor to the high threshold setting just before the Flash write
operation and then changing it back to the low threshold setting immediately after the Flash write opera-
tion).
The following note applies to Revision C devices: The output of the internal voltage regulator (REG0) is
calibrated by the MCU immediately after a power-on reset (POR). This calibrated output setting will stay
calibrated through any type of reset other than POR. Because of this change in behavior of REG0, the “l(fā)ow
threshold” recommendation noted above for Revision A and Revision B devices does not apply to Revision
C devices; the VDD Monitor (VDDMON0) can be set to the high threshold as needed depending on the
application.
20.6. Reset Low Time
The maximum reset low time differs between the silicon revisions of C8051F52x/52xA/F53x/F53xA
devices.
Reset low time is the duration for which the RST pin is driven low by an external circuit while power is
applied to the device. On Revision A and Revision B devices with assembly build date code earlier than
1124 (year 2011, work week 24), the reset low time should be a maximum of 1 second. For longer reset
low times, a percentage of devices within a narrow range of temperatures (a 5 to 10 C window) may
“l(fā)ock up” and fail to execute code. The condition is cleared only by cycling power.
Revision B devices with assembly date code 1124 or later and Revision C devices do not have any restric-
tions on reset low time.
20.7. Internal Oscillator Suspend Mode
The required bias setting for the internal oscillator before entering suspend mode differs between the sili-
con revisions of C8051F52x/52xA/F53x/F53xA devices.
On Revision A and Revision B devices, firmware must set the ZTCEN bit in REF0CN (SFR Definition 5.1)
before entering suspend mode. If ZTCEN is not set to 1, there is a low probability of the device remaining
in suspend even when a wake-up condition is triggered. On Revision C devices, this bit need not be set to
1 before entering suspend mode.
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