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| 型號(hào)： | TOOLSTICK410PP |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 106/270頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | ADAPTER PROGRAM TOOLSTICK F410 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ToolStick |
| 類型： | 微控制器編程器 |
| 適用于相關(guān)產(chǎn)品： | C8051F410/412 |
| 所含物品： | 2 個(gè)板和 USB 連接線纜 |
| 產(chǎn)品目錄頁(yè)面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 336-1310-ND - IC 8051 MCU 16K FLASH 32LQFP 336-1318-ND - IC 8051 MCU 32K FLASH 32LQFP |
| 其它名稱： | 336-1453 |
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C8051F410/1/2/3
194
Rev. 1.1
21.3.3. SCL Low Timeout
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-
cation no later than 10 ms after detecting the timeout condition.
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
21.3.4. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 s, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods. If the SMBus is waiting to generate a
Master START, the START will be generated following this timeout. Note that a clock source is required for
free timeout detection, even in a slave-only implementation.
Enabling the Bus Free Timeout is recom-
mended.
21.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
SMBus interrupts are generated for each data byte or slave address that is transferred. When transmitting,
this interrupt is generated after the ACK cycle so that software may read the received ACK value; when
receiving data, this interrupt is generated before the ACK cycle so that software may define the outgoing
ACK value. See Section “21.5. SMBus Transfer Modes” on page 201 for more details on transmission
sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in
“21.4.2. SMB0CN Control Register” on page 198; Table 21.4 provides a quick SMB0CN decoding refer-
ence.
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