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參數(shù)資料
| 型號： | TOOLSTICK330PP |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 48/226頁 |
| 文件大?。?/td> | 0K |
| 描述： | ADAPTER PROGRAM TOOLSTICK F330 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ToolStick |
| 類型： | 微控制器編程器 |
| 適用于相關(guān)產(chǎn)品： | C8051F330/331/332/333/334/335/336/337 |
| 所含物品： | 2 個(gè)板和 USB 連接線纜 |
| 相關(guān)產(chǎn)品： | 336-1429-5-ND - IC MCU 16K FLASH 20QFN 336-1428-5-ND - IC MCU 16K FLASH 20QFN C8051F335-GMR-ND - IC 8051 MCU 2K FLASH 20MLP C8051F334-GMR-ND - IC 8051 MCU 2K FLASH 20MLP C8051F333-GMR-ND - IC 8051 MCU 4K FLASH 20MLP C8051F332-GMR-ND - IC 8051 MCU 4K FLASH 20MLP C8051F331-GMR-ND - IC 8051 MCU 8K FLASH 20QFN C8051F330-GMR-ND - IC 8051 MCU 8K FLASH 20MLP 336-1269-ND - IC 8051 MCU 2KB FLASH 20QFN 336-1268-ND - IC 8051 MCU 2KB FLASH 20QFN 更多... |
| 其它名稱： | 336-1451 |
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Rev.1.0
141
C8051F336/7/8/9
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable
and re-enable) the SMBus in the event of an SCL low timeout.
21.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 s, the bus
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only implemen-
tation.
21.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides
the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-
ware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data, receiving
an ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;
when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated before the
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,
these interrupts are always generated after the ACK cycle. See Section 21.5 for more details on transmis-
sion sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. The SMB0CN register is described in Section 21.4.2;
Table 21.5 provides a quick SMB0CN decoding reference.
21.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
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