參數(shù)資料
型號(hào)： TN83C196MD
廠商： Intel Corp.
英文描述： INDUSTRIAL MOTOR CONTROL MICROCONTROLLER
中文描述： 工業(yè)電機(jī)控制微控制器
文件頁(yè)數(shù)： 4/25頁(yè)
文件大?。?/td> 1062K
代理商： TN83C196MD
8XC196MD
8XC196MC AND 8XC196MD
DIFFERENCES
INTDMASK1/INTDPEND1 Registers
There
8XC196MC
INTDPEND1 registers. The 8XC196MD interrupt
mask and pending registers are shown below. No-
tice that the CAPCOM5, COMP4, and CAPCOM4
bits are reserved bits on the 8XC196MC. The PI bit
of the INTDPEND1 register will be set when a
Waveform Generator or Compare Module 5 event
occurs and the corresponding bit in the PIDMASK
register is set. The PI interrupt vector can be taken
when the PI bit in the INTDMASK1 register is set.
The 8XC196MC User’s Manual should be refer-
enced for details about the interrupts.
are
some
and
differences
8XC196MD
between
INTDMASK1/
the
INTDMASK1 (0031H)
and INTDPEND1 (0012H)
5
4
7
6
3
2
1
0
RSV EXTINT
PI
CAPCOM5
*
COMP4
*
CAPCOM4
*
COMP3 CAPCOM3
RSV
e
RESERVED BIT. MUST WRITE AS 0
*
e
THIS BIT RESERVED ON 8XC196MC.
Figure 3. Interrupt Mask and Status Registers
PTSSRV and PTSSEL Register
Similarly, there are differences between 8XC196MC
and 8XC196MD PTS registers. The 8XC196MD PTS
registers are shown below. Notice the CAPCOM5,
COMP4, and CAPCOM4 bits are reserved bits on
the 8XC196MC. The PI bit in the PTSSRV will be set
when a Waveform Generator or Compare Module 5
end of PTS interrupt occurs and the corresponding
bit in the PIDMASK register is set. The PI PTS vec-
tor can be used when the PI bit in the PTSSEL regis-
ter is set. The 8XC196MC User’s Manual should be
referenced for details about the PTS.
PTSSEL (0004H) and PTSSRV (0006H)
15
14
13
12
11
10
9
8
RSV
EXTINT
PI
CAPCOM5
*
COMP4
*
CAPCOM4
*
COMP3 CAPCOM3
7
6
5
4
3
2
1
0
COMP2 CAPCOM2 COMP1 CAPCOM1 COMP0 CAPCOM0 ADDDONE TOVF
RSV
e
RESERVED BIT. MUST WRITE AS 0
*
e
THIS BIT RESERVED ON 8XC196MC.
Figure 4. PTS Select and Service Registers
PIDMASK and PIDPEND Registers
The PIDMASK/PIDPEND registers contain the bits
for the Compare Module 5 (COMP5) Waveform Gen-
erator (WG), Timer 1 Overflow (TFI), and Timer 2
Overflow (TF2) mask/status flag. The diagram be-
low shows the registers. Notice that the COMP5 bit
is a reserved bit on the 8XC196MC. The 8XC196MC
User’s Manual should be referenced for details
about the Waveform Generator, Compare Modules,
and Timers.
PIDMASK (1FBEH) and
PIDPEND (1FBCH, Read Only)
6
5
4
7
3
2
1
0
RSV
COMP5
*
RSV
WG
RSV
TF2
RSV
TF1
RSV
e
RESERVED BIT. MUST WRITE AS 0,
READ AS 1.
*
e
THIS BIT RESERVED ON 8XC196MC.
Figure 5. Peripheral Interrupt Mask
and Status Registers
The PI bit in the INTDPEND1 register is set if a
Waveform Generator event or Compare Module 5
event occurs and the corresponding PIDMASK bit is
set. For either of these events to cause an interrupt,
the PI bit in the INTDMASK1 register and the corre-
sponding event bit in the PIDMASK register must be
set.
Similarly, the TOVF bit in the INTDPEND register is
set if Timer 1 or Timer 2 overflow and the corre-
sponding bit in the PIDMASK register is set. For ei-
ther of these two events to cause an interrupt, the
TOVF bit in the INTDMASK register and the corre-
sponding event bit in the PIDMASK must be set.
Upon a PI and/or a TOVF interrupt, it may be neces-
sary to check if the Compare Module 5, the Wave-
form Generator, Timer 1, or Timer 2 event caused
the interrupt. The PIDPEND will give this informa-
tion. However, it should be noted that reading the
PIDPEND register will clear the register. So the indi-
vidual bits in the PIDPEND register must be read by
loading PIDPEND into another ‘‘shadow’’ register,
then checking the ‘‘shadow’’ register to see what
event occurred.
4
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