參數(shù)資料
型號: TMX320F2811ZHHS
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812數(shù)字信號處理器
文件頁數(shù): 90/147頁
文件大小: 2021K
代理商: TMX320F2811ZHHS
Electrical Specifications
90
June 2004
SPRS257
6.12
Device Clock Table
This section provides the timing requirements and switching characteristics for the various clock options
available on R281x DSPs. Table 6
2 lists the cycle times of various clocks.
Table 6
2. TMS320R281x Clock Table and Nomenclature
MIN
28.6
NOM
MAX
UNIT
ns
On chip oscillator clock
On-chip oscillator clock
t
c(OSC)
, Cycle time
Frequency
50
20
35
MHz
XCLKIN
t
c(CI)
, Cycle time
Frequency
6.67
250
ns
4
150
MHz
SYSCLKOUT
t
c(SCO)
, Cycle time
Frequency
6.67
500
ns
2
150
MHz
XCLKOUT
t
c(XCO)
, Cycle time
Frequency
6.67
2000
ns
0.5
150
MHz
HSPCLK
t
c(HCO)
, Cycle time
Frequency
6.67
13.3
75
26.6
37.5
ns
150
MHz
LSPCLK
t
c(LCO)
, Cycle time
Frequency
t
c(ADCCLK)
, Cycle time
Frequency
13.3
ns
75
MHz
ADC clock
40
ns
25
MHz
SPI clock
t
c(SPC)
, Cycle time
Frequency
50
ns
20
MHz
McBSP
t
c(CKG)
, Cycle time
Frequency
50
ns
20
MHz
XTIMCLK
t
c(XTIM)
, Cycle time
Frequency
6.67
ns
150
MHz
The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower.
ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT.
This is the default reset value if SYSCLKOUT = 150 MHz.
6.13
Clock Requirements and Characteristics
6.13.1
Input Clock Requirements
The clock provided at the XCLKIN pin generates the internal CPU clock cycle.
Table 6
3. Input Clock Frequency
PARAMETER
MIN
20
20
TYP
MAX
UNIT
Resonator
Crystal
XCLKIN
35
35
150
f
x
Input clock frequency
MHz
4
f
l
Limp mode clock frequency
2
MHz
A
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