參數(shù)資料
型號： TMX320F2811GHHA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 69/147頁
文件大小： 2021K
代理商： TMX320F2811GHHA
Peripherals
69
June 2004
SPRS257
Table 4
7 provides a summary of the McBSP registers.
Table 4
7. McBSP Register Summary
NAME
ADDRESS
0x00 78xxh
TYPE
(R/W)
DATA REGISTERS, RECEIVE, TRANSMIT
0x0000
0x0000
0x0000
RESET VALUE
(HEX)
DESCRIPTION
McBSP Receive Buffer Register
McBSP Receive Shift Register
McBSP Transmit Shift Register
McBSP Data Receive Register 2
Read First if the word size is greater than 16 bits,
else ignore DRR2
DRR2
00
R
0x0000
DRR1
01
R
0x0000
McBSP Data Receive Register 1
Read Second if the word size is greater than 16 bits,
else read DRR1 only
DXR2
02
W
0x0000
McBSP Data Transmit Register 2
Write First if the word size is greater than 16 bits,
else ignore DXR2
DXR1
03
W
0x0000
McBSP Data Transmit Register 1
Write Second if the word size is greater than 16 bits,
else write to DXR1 only
McBSP CONTROL REGISTERS
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
MULTICHANNEL CONTROL REGISTERS
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
R/W
0x0000
SPCR2
SPCR1
RCR2
RCR1
XCR2
XCR1
SRGR2
SRGR1
04
05
06
07
08
09
0A
0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
McBSP Serial Port Control Register 2
McBSP Serial Port Control Register 1
McBSP Receive Control Register 2
McBSP Receive Control Register 1
McBSP Transmit Control Register 2
McBSP Transmit Control Register 1
McBSP Sample Rate Generator Register 2
McBSP Sample Rate Generator Register 1
MCR2
MCR1
RCERA
RCERB
XCERA
XCERB
PCR1
RCERC
RCERD
XCERC
XCERD
0C
0D
0E
0F
10
11
12
13
14
15
16
McBSP Multichannel Register 2
McBSP Multichannel Register 1
McBSP Receive Channel Enable Register Partition A
McBSP Receive Channel Enable Register Partition B
McBSP Transmit Channel Enable Register Partition A
McBSP Transmit Channel Enable Register Partition B
McBSP Pin Control Register
McBSP Receive Channel Enable Register Partition C
McBSP Receive Channel Enable Register Partition D
McBSP Transmit Channel Enable Register Partition C
McBSP Transmit Channel Enable Register Partition D
DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode.
FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers.
A
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