參數(shù)資料
型號(hào)： TMX320F28069PFPA
廠商： Texas Instruments
文件頁數(shù)： 114/174頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 128KB FLASH 80LQFP
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Piccolo F2806x
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 1
系列： TMS320F2806x, Piccolo™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 40
程序存儲(chǔ)器容量： 256KB（128K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 50K x 16
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP 裸露焊盤
包裝： 托盤
其它名稱： 296-32777
TMX320F28069PFPA-ND
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
2.8
VREG, BOR, POR
Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip
voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and
space of a second external regulator on an application board. Additionally, internal power-on reset (POR)
and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode.
2.8.1
On-chip Voltage Regulator (VREG)
A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors
are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins
to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the
primary concern of the application.
2.8.1.1
Using the On-chip VREG
To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended
operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by
the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum)
capacitance for proper regulation of the VREG. These capacitors should be located as close as possible
to the VDD pins.
2.8.1.2
Disabling the On-chip VREG
To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to
the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied
high.
2.8.2
On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit
Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the
burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is
to create a clean reset throughout the device during the entire power-up procedure. The trip point is a
looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device
operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device power-
up, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled
(VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their
respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage
protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4 for the various trip
points as well as the delay time for the device to release the XRS pin after the under-voltage or over-
voltage condition is removed. Figure 2-10 shows the VREG, POR, and BOR. To disable both the VDD and
VDDIO BOR functions, a bit is provided in the BORCFG register. See the "Systems Control and Interrupts"
chapter of the TMS320x2806x Piccolo Technical Reference Manual (literature number SPRUH18) for
details.
44
Device Overview
Copyright 2010–2012, Texas Instruments Incorporated
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