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TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
List of Figures
2-1
100-Pin PZ LQFP (Top View)
 ...................................................................................................
 12
100-Ball GGM and ZGM MicroStar BGA (Bottom View)
..................................................................
 13
Functional Block Diagram
........................................................................................................
 20
F28044 Memory Map
.............................................................................................................
 21
External and PIE Interrupt Sources
.............................................................................................
 31
Multiplexing of Interrupts Using the PIE Block
 ................................................................................
 32
Clock and Reset Domains
.......................................................................................................
 34
OSC and PLL Block Diagram
 ...................................................................................................
 36
Using a 3.3-V External Oscillator
 ...............................................................................................
 36
Using a 1.8-V External Oscillator
 ...............................................................................................
 36
Using the Internal Oscillator
 .....................................................................................................
 36
Watchdog Module
.................................................................................................................
 39
CPU-Timers
........................................................................................................................
 41
CPU-Timer Interrupt Signals and Output Signal
..............................................................................
 42
Multiple PWM Modules
...........................................................................................................
 43
ePWM Sub-Modules Showing Critical Internal Signal Interconnections
...................................................
 48
Block Diagram of the ADC Module
.............................................................................................
 50
ADC Pin Connections With Internal Reference
...............................................................................
 51
ADC Pin Connections With External Reference
..............................................................................
 52
Serial Communications Interface (SCI) Module Block Diagram
 ............................................................
 56
SPI Module Block Diagram (Slave Mode)
 .....................................................................................
 59
I
2
C Peripheral Module Interfaces
 ...............................................................................................
 61
GPIO MUX Block Diagram
.......................................................................................................
 62
Qualification Using Sampling Window
..........................................................................................
 65
Example of TMS320x280x Device Nomenclature
............................................................................
 67
Emulator Connection Without Signal Buffering for the DSP
.................................................................
 75
3.3-V Test Load Circuit
...........................................................................................................
 77
Clock Timing
.......................................................................................................................
 79
Power-on Reset
...................................................................................................................
 80
Warm Reset
........................................................................................................................
 81
Example of Effect of Writing Into PLLCR Register
 ...........................................................................
 82
General-Purpose Output Timing
................................................................................................
 82
Sampling Mode
....................................................................................................................
 83
General-Purpose Input Timing
 ..................................................................................................
 84
IDLE Entry and Exit Timing
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 85
STANDBY Entry and Exit Timing Diagram
....................................................................................
 86
HALT Wake-Up Using GPIOn
...................................................................................................
 87
PWM Hi-Z Characteristics
 .......................................................................................................
 88
ADCSOCAO or ADCSOCBO Timing
...........................................................................................
 89
2-2
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
List of Figures
4
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