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  • 參數(shù)資料
    型號: TMX320C6211GHK167
    廠商: Texas Instruments, Inc.
    元件分類: 數(shù)字信號處理
    英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
    中文描述: 定點數(shù)字信號處理器
    文件頁數(shù): 37/83頁
    文件大?。?/td> 1176K
    代理商: TMX320C6211GHK167
    TMS320C6211, TMS320C6211B
    FIXED-POINT DIGITAL SIGNAL PROCESSORS
    SPRS073K
    AUGUST 1998
    REVISED MARCH 2004
    37
    POST OFFICE BOX 1443
    HOUSTON, TEXAS 77251
    1443
    power-supply sequencing
    TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
    systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
    supply is below the proper operating voltage.
    system-level design considerations
    System-level design considerations, such as bus contention, may require supply sequencing to be
    implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
    down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
    output buffers are powered up, thus, preventing bus contention with other chips on the board.
    power-supply design considerations
    For systems using the C6000
    DSP platform of devices, the core supply may be required to provide in excess
    of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
    within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
    I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
    PLL disabled, as many as five external clock cycle pulses may be required to stop this extra current draw. A
    normal current state returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing
    the amount of time between the core supply power up and the I/O supply power up can minimize the effects
    of this current draw.
    A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
    plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the
    Using the
    TPS56300 to Power DSPs
    application report (literature number SLVA088)]. A Schottky diode can also be used
    to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
    logic within the DSP.
    Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
    inductance and resistance in the power delivery path. Additionally, when designing for high-performance
    applications utilizing the C6000
    platform of DSPs, the PC board should include separate power planes for
    core, I/O, and ground, all bypassed with high-quality low-ESL/ESR capacitors.
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