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參數資料
| 型號： | TMX320C6211BGJC100 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點數字信號處理器 |
| 文件頁數： | 46/70頁 |
| 文件大小： | 1050K |
| 代理商： | TMX320C6211BGJC100 |
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
HOLD/HOLDA TIMING
timing requirements for the HOLD/HOLDA cycles
(see Figure 27)
NO.
200
UNIT
MIN
MAX
3
t
oh(HOLDAL-HOLDL)
Output hold time, HOLD low after HOLDA low
P
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
switching characteristics over recommended operating conditions for the HOLD/HOLDA cycles
(see Figure 27)
NO.
PARAMETER
200
UNIT
MIN
4P
MAX
1
2
4
5
t
d(HOLDL-EMHZ)
t
d(EMHZ-HOLDAL)
t
d(HOLDH-EMLZ)
t
d(EMLZ-HOLDAH)
Delay time, HOLD low to EMIF Bus high impedance
Delay time, EMIF Bus high impedance to HOLDA low
Delay time, HOLD high to EMIF Bus low impedance
Delay time, EMIF Bus low impedance to HOLDA high
§
ns
ns
ns
ns
0
2P
7P
2P
3P
0
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
§
All pending EMIF transactions are allowed to complete before HOLDA is asserted. The worst case for this is an asynchronous read or write with
external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 = 1. If no bus transactions are occurring, then the
minimum delay time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
HOLD
HOLDA
EMIF Bus
DSP Owns Bus
External Requestor
Owns Bus
DSP Owns Bus
C6205
C6205
1
3
2
5
4
EMIF Bus consists of CE[3:0], BE[3:0], ED[31:0], EA[21:2], ARE, AOE, AWE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE, and SDA10.
Figure 27. HOLD/HOLDA Timing
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