參數(shù)資料
型號(hào)： TMX320C2812PGFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號(hào)處理器
文件頁數(shù)： 119/147頁
文件大?。?/td> 2021K
代理商： TMX320C2812PGFA
Electrical Specifications
119
June 2004
SPRS257
Lead
Active
Trail
DIN
t
d(XCOH-XZCSL)
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XZCSH)
t
d(XCOHL-XRDH)
WS (Synch)
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
XREADY(Synch)
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes
alignment cycles.
D. For each sample, setup time from the beginning of the access (D) can be calculated as:
D = (XRDLEAD + XRDACTIVE +n
1) t
c(XTIM)
t
su(XRDYsynchL)XCOHL
E. Reference for the first sample is with respect to this point
E = (XRDLEAD + XRDACTIVE) t
c(XTIM)
where n is the sample number: n = 1, 2, 3, and so forth.
t
h(XRDYsynchL)
t
su(XRDHsynchH)XCOHL
t
su(XRDYsynchL)XCOHL
t
su(XD)XRD
t
a(XRD)
t
a(A)
t
h(XD)XRD
t
h(XRDYsynchH)XZCSH
= Don’t care. Signal can be high or low during this time.
Legend:
See Note D
See Note E
t
e(XRDYsynchH)
See Notes A and B
See Note C
Figure 6
28. Example Read With Synchronous XREADY Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
XWRACTIVE
XWRTRAIL
READYMODE
≥
1
3
≥
1
1
0
N/A
N/A
N/A
0 = XREADY
(Synch)
N/A = “Don’t care” for this example
A
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