參數(shù)資料
型號: TMSH
廠商: Xilinx, Inc.
英文描述: XC1800 Series of In-System Programmable Configuration PROMs
中文描述: XC1800系列在系統(tǒng)可編程配置PROM的
文件頁數(shù): 3/16頁
文件大?。?/td> 117K
代理商: TMSH
R
September 17, 1999 (Version 1.3)
3
XC1800 Series of In-System Programmable Configuration PROMs
*Programmable for Serial Mode only on 18512 and 1801.
CEO
13
DATA OUT Chip Enable (CEO) output is connected
to the CE input of the next PROM in the
chain. This output is Low when the CE
and OE/RESET inputs are active AND
the internal address counter has been in-
cremented beyond its Terminal Count
(TC) value. When the PROM has been
read, CEO will follow CE as long as OE/
RESET is High. When OE/RESET goes
Low, CEO stays High until the PROM is
brought out of reset by bringing OE/RE-
SET High. CEO can be programmed to
be either active High or active Low.
21
27
13
14
OUTPUT
ENABLE
GND
GND is the ground connection.
6, 18, 28 &
41
3, 12, 24 &
34
11
TMS
MODE
SELECT
The state of TMS on the rising edge of
TCK determines the state transitions at
the Test Access Port (TAP) controller.
TMS has an internal 50K ohm resistive
pull-up on it to provide a logic 1 to the de-
vice if the pin is not driven.
5
11
5
TCK
CLOCK
This pin is the JTAG test clock. It se-
quences the TAP controller and all the
JTAG test and programming electronics.
7
13
6
TDI
DATA IN
This pin is the serial input to all JTAG in-
struction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic 1 to the system if the pin is
not driven.
3
9
4
TDO
DATA OUT This pin is the serial output for all JTAG
instruction and data registers. TDO has
an internal 50k ohm resistive pull-up on it
to provide a logic 1 to the system if the pin
is not driven.
31
37
17
V
CC
Positive voltage supply of 3.3V for inter-
nal logic and input buffers.
17, 35 & 38
23, 41 & 44
18 & 20
V
CCO
Positive voltage supply connected to the
output voltage drivers.
8, 16, 26 &
36
14, 22, 32 &
42
19
Pin
Name
Boundary
Scan
Order
Function
Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC & PLCC
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