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參數(shù)資料
| 型號： | TMS46400PDGA |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576字4位動(dòng)態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大小： | 657K |
| 代理商： | TMS46400PDGA |
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS at V
IL
after a read operation and cycling RAS after a specified
precharge period, similar to a RAS-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CHR
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300-
μ
A (TMS46400P) or 500-
μ
A
(TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125
μ
s while holding RAS low for less than 1
μ
s. To minimize current consumption, all
input levels need to be at CMOS levels (V
IL
≤
0.2 V, V
IH
≥
V
CC
– 0.2 V).
self refresh
The self-refresh mode is entered by dropping CAS low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100
μ
s. The chip is then refreshed by an on-board oscillator. No external address is required
since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS and CAS
are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation, to ensure that the DRAM is fully
refreshed.
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
test mode
The test mode is initiated with a CBR refresh cycle while simultaneously holding W low (WCBR). The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device
exits test mode if a CBR refresh cycle with W held high or a RAS-only refresh (ROR) cycle is performed.
The TMS4x400/P is configured as a 512K
×
8 bit device in test mode, where each DQ pin has a separate 2-bit
parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin
separately. If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to
reflect the state of their respective DQ pins during a parallel-write operation. Each DQ pin is independent of the
others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for
this series.
A
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