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| 型號： | TMS44400PDJ |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576字4位動態(tài)隨機存取記憶體 |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 657K |
| 代理商： | TMS44400PDJ |
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
10
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4x400-60
’4x400P-60
’4x400-70
’4x400P-70
’4x400-80
’4x400P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tROH
tAWD
tCHR
tCRP
tCSH
tCSR
tCWD
tRAD
tRAL
tCAL
tRCD
tRPC
tRSH
tRWD
tTAA
tTCPA
tTRAC
Hold time, RAS referenced to OE
10
10
10
ns
Delay time, column address to W low (read-write operation only)
55
63
70
ns
Delay time, RAS low to CAS high (CBR refresh only)
10
10
10
ns
Delay time, CAS high to RAS low
0
0
0
ns
Delay time, RAS low to CAS high
60
70
80
ns
Delay time, CAS low to RAS low (CBR refresh only)
5
5
5
ns
Delay time, CAS low to W low (read-write operation only)
40
46
50
ns
Delay time, RAS low to column address (see Note 15)
15
30
15
35
15
40
ns
Delay time, column address to RAS high
30
35
40
ns
Delay time, column address to CAS high
30
35
40
ns
Delay time, RAS low to CAS low (see Note 15)
20
45
20
52
20
60
ns
Delay time, RAS high to CAS low
0
0
0
ns
Delay time, CAS low to RAS high
15
18
20
ns
Delay time, RAS low to W low (read-write operation only)
85
98
110
ns
Access time from address (test mode)
35
40
45
ns
Access time from column precharge (test mode)
40
45
50
ns
Access time from RAS (test mode)
65
75
85
ns
tREF
Refresh time interval
’4x400
16
16
16
ms
’4x400P
128
128
128
ms
tT
Transition time
2
30
2
30
2
30
ns
NOTE 15: The maximum value is specified only to ensure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V
VCC = 5 V
CL = 100 pF
(see Note A)
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
(b) ALTERNATE LOAD CIRCUIT
(a) LOAD CIRCUIT
RL = 218
R1 = 828
R2 = 295
NOTE A: CL includes probe and fixture capacitance.
Figure 2. Load Circuits for Timing Parameters
A
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