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| 型號(hào)： | TMS44400PDGA |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 1048576-WORD BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 1048576字4位動(dòng)態(tài)隨機(jī)存取記憶體 |
| 文件頁數(shù)： | 9/25頁 |
| 文件大小： | 657K |
| 代理商： | TMS44400PDGA |
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
9
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4x400-60
’4x400P-60
’4x400-70
’4x400P-70
’4x6400-80
’4x400P-80
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
tRWC
tPC
tPRWC
tRASP
tRAS
tRASS
tCAS
tCP
tRP
tRPS
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWSR
tWTS
tCAH
tDHR
tDH
tAR
tRAH
tRCH
tRRH
tWCH
tWCR
tWHR
tWTH
tCHS
tOEH
tOED
NOTES:
Cycle time, random read or write (see Note 8)
110
130
150
ns
Cycle time, read-write
155
181
205
ns
Cycle time, page-mode read or write (see Note 9)
40
45
50
ns
Cycle time, page-mode read-write
85
96
105
ns
Pulse duration, RAS low, page mode (see Note 10)
60
100 000
70
100 000
80
100 000
ns
Pulse duration, RAS low, nonpage mode (see Note 10)
60
10 000
70
10 000
80
10 000
ns
μ
s
ns
Pulse duration, RAS low, self refresh
100
100
100
Pulse duration, CAS low (see Note 11)
10
10 000
18
10 000
20
10 000
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Precharge time after self refresh using RAS
110
130
150
ns
Pulse duration, write
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data (see Note 12)
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
Setup time, W low before CAS high
15
18
20
ns
Setup time, W low before RAS high
15
18
20
ns
Setup time, W low before CAS low (early-write operation only)
0
0
0
ns
Setup time, W high (CBR refresh only)
10
10
10
ns
Setup time, W low (test mode only)
10
10
10
ns
Hold time, column address after CAS low
10
15
15
ns
Hold time, data after RAS low (see Note 13)
50
55
60
ns
Hold time, data (see Note 12)
10
15
15
ns
Hold time, column address after RAS low (see Note 13)
50
55
60
ns
Hold time, row address after RAS low
10
10
10
ns
Hold time, W high after CAS high (see Note 14)
0
0
0
ns
Hold time, W high after RAS high (see Note 14)
0
0
0
ns
Hold time, W low after CAS low (early-write operation only)
10
15
15
ns
Hold time, W low after RAS low (see Note 13)
50
55
60
ns
Hold time, W high (CBR refresh only)
10
10
10
ns
Hold time, W low (test mode only)
10
10
10
ns
Hold time, CAS low after RAS high (self refresh)
– 50
– 50
– 50
ns
Hold time, OE command
15
18
20
ns
Hold time, OE to data delay
15
18
20
ns
8. All cycle times assume tT = 5 ns.
9. To ensure tPC min, tASC should be
≥
tCP.
10. In a read-write cycle, tRWD and tRWL must be observed.
11. In a read-write cycle, tCWD and tCWL must be observed.
12. Referenced to the later of CAS or W in write operations
13. The minimum value is measured when tRCD is set to tRCD min as a reference.
14. Either tRRH or tRCH must be satisfied for a read cycle.
A
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