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參數(shù)資料
| 型號： | TMS427400 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS |
| 中文描述： | 4194304 - Word的4位高速DRAM等 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大小： | 441K |
| 代理商： | TMS427400 |
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TMS416400, TMS416400P, TMS417400, TMS417400P
TMS426400, TMS426400P, TMS427400, TMS427400P
4194304-WORD BY 4-BIT HIGH-SPEED DRAMS
SMKS881B – MAY 1995 – REVISED AUGUST 1995
3
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
RAS-only refresh
TMS4x6400, TMS4x6400P
A refresh operation must be performed at least once every 64 ms (128 ms for TMS4x6400P) to retain data. This
can be achieved by strobing each of the 4096 rows (A0–A11). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
TMS4x7400, TMS4x7400P
A refresh operation must be performed at least once every 32 ms (128 ms for TMS4x7400P) to retain data. This
can be achieved by strobing each of the 2048 rows (A0–A10). A normal read or write cycle refreshes all bits
in each row that is selected. A RAS-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffers remain in the high-impedance state. Externally generated addresses
must be used for a RAS-only refresh.
hidden refresh
Hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding
CAS at V
IL
after a read operation and cycling RAS after a specified precharge period, similar to a RAS-only
refresh cycle. The external address is ignored, and the refresh address is generated internally.
CAS-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CHR
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored, and the refresh address is generated internally.
battery-backup refresh
TMS4x6400P
A low-power battery-backup refresh mode that requires less than 500
μ
A (5 V) or 350
μ
A (3.3 V) refresh current
is available on the TMS4x6400P. Data integrity is maintained using CBR refresh with a period of 31.25
μ
s while
holding RAS low for less than 1
μ
s. To minimize current consumption, all input levels must be at CMOS levels
( V
IL
<
0.2 V, V
IH
>
V
CC
– 0.2 V).
TMS4x7400P
A low-power battery-backup refresh mode that requires less than 500
μ
A (5 V) or 350
μ
A (3.3 V) refresh current
is available on the TMS4x7400P. Data integrity is maintained using CBR refresh with a period of 62.5
μ
s while
holding RAS low for less than 1
μ
s. To minimize current consumption, all input levels must be at CMOS levels
(V
IL
<
0.2 V, V
IH
>
V
CC
– 0.2 V).
self refresh (TMS4xx400P)
The self-refresh mode is entered by dropping CAS low prior to RAS going low. Then CAS and RAS are both
held low for a minimum of 100
μ
s. The chip is then refreshed internally by an on-board oscillator. No external
address is required because the CBR counter is used to keep track of the address. To exit the self-refresh mode,
both RAS and CAS are brought high to satisfy t
CHS
. Upon exiting self-refresh mode, a burst refresh (refresh a
full set of row addresses) must be executed before continuing with normal operation. The burst refresh ensures
the DRAM is fully refreshed.
power up
To achieve proper device operation, an initial pause of 200
μ
s followed by a minimum of eight initialization cycles
is required after power up to the full V
CC
level. These eight initialization cycles must include at least one refresh
(RAS-only or CBR) cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS427400P | 4194304-WORD BY 4-BIT HIGH-SPEED DRAMS |
| TMS416409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS417409ADJ-60 | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS417409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS426409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS427400P | 制造商:TI 制造商全稱:Texas Instruments 功能描述:4194304-WORD BY 4-BIT HIGH-SPEED DRAMS |
| TMS427409A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS427409ADGA-60 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS428160 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576-WORD BY 16-BIT HIGH-SPEED DRAMS |
| TMS428160P | 制造商:TI 制造商全稱:Texas Instruments 功能描述:1048576-WORD BY 16-BIT HIGH-SPEED DRAMS |
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