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| 型號(hào)： | TMS416409A |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| 中文描述： | 4194304 4位擴(kuò)展數(shù)據(jù)輸出動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 |
| 文件頁(yè)數(shù)： | 15/37頁(yè) |
| 文件大?。?/td> | 515K |
| 代理商： | TMS416409A |
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TMS416409A, TMS417409A, TMS426409A, TMS427409A
4194304 BY 4-BIT EXTENDED DATA OUT
DYNAMIC RANDOM-ACCESS MEMORIES
SMKS893B – AUGUST 1996 – REVISED APRIL 1997
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4)
’41x409A-50
’42x409A-50
’41x409A-60
’42x409A-60
’41x409A-70
’42x409A-70
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tRC
tRWC
tRASP
tRAS
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
Cycle time, random read or write
84
104
124
ns
Cycle time, read-write
111
135
160
ns
Pulse duration, RAS active, fast page mode (see Note 8)
50
100 000
60
100 000
70
100 000
ns
Pulse duration, RAS active, non-page mode (see Note 8)
50
10 000
60
10 000
70
10 000
ns
Pulse duration, RAS precharge
30
40
50
ns
Pulse duration, write command
8
10
10
ns
Setup time, column address
0
0
0
ns
Setup time, row address
0
0
0
ns
Setup time, data in (see Note 9)
0
0
0
ns
Setup time, read command
0
0
0
ns
Setup time, write command before CAS precharge
8
10
12
ns
Setup time, write command before RAS precharge
8
10
12
ns
tWCS
Setup time, write command before CAS active
(early-write only)
0
0
0
ns
tWRP
tWTS
tCSR
tCAH
tDH
tRAH
tRCH
tRRH
Setup time, W high before RAS low (CBR refresh only)
10
10
10
ns
Setup time, W low before RAS low (test mode only)
10
10
10
ns
Setup time, CAS referenced to RAS (CBR refresh only)
5
5
5
ns
Hold time, column address
8
10
12
ns
Hold time, data in (see Note 9)
8
10
12
ns
Hold time, row address
8
10
10
ns
Hold time, read command referenced to CAS (see Note 10)
0
0
0
ns
Hold time, read command referenced to RAS (see Note 10)
0
0
0
ns
tWCH
Hold time, write command during CAS active
(early-write only)
8
10
12
ns
tROH
tWRH
tWTH
tCHR
tOEH
tRHCP
NOTES:
Hold time, RAS referenced to OE
8
10
10
ns
Hold time, W high after RAS low (CBR refresh)
10
10
10
ns
Hold time, W low after RAS low (test mode only)
10
10
10
ns
Hold time, CAS referenced to RAS (CBR refresh only)
10
10
10
ns
Hold time, OE command
13
15
18
ns
Hold time, RAS active from CAS precharge
28
35
40
ns
4. With ac parameters, it is assumed that tT = 2 ns.
8. In a read-write cycle, tRWD and tRWL must be observed.
9. Referenced to the later of CAS or W in write operations
10. Either tRRH or tRCH must be satisfied for a read cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS417409ADJ-60 | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS417409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS426409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS427409A | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
| TMS427409ADGA-60 | 4194304 BY 4-BIT EXTENDED DATA OUT DYNAMIC RANDOM-ACCESS MEMORIES |
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