
TMS370Cx9x
8-BIT MICROCONTROLLER
SPNS036B –  JANUARY 1996 – REVISED FEBRUARY 1997
16
POST OFFICE BOX 1443 
 HOUSTON, TEXAS 77251–1443
clock modules
The ‘370Cx9x family provides two clock options which are referred to as divide-by-1 (PLL) and divide-by-4
(standard oscillator). Both the divide-by-1 and divide-by-4 options are configurable during the manufacturing
process of a TMS370 microcontroller. The ‘370C090A ROM-masked devices offer both options to meet system
engineering requirements. Only one of the two clock options is allowed on the ROM device while the EPROM
device ’792 has only the divide-by-4 clock.
The divide-by-1 clock module option provides the capability for reduced electromagnetic interference (EMI) with
no added cost.
The divide-by-1 provides a 1-to-1 match of the external resonator frequency (CLKIN) to the internal system clock
(SYSCLK) frequency. The divide-by-4 produces a SYSCLK which is one-fourth the frequency of the external
resonator. Inside the divide-by-1 module, the frequency of the external resonator is multiplied by four. The clock
module then divides the resulting signal by four to provide the four-phased internal system clock signals. The
resulting SYSCLK is equal to the resonator frequency. The frequencies are formulated as follows:
Divide-by-4 option : SYSCLK
external resonator frequency
4
external resonator frequency
CLKIN
4
Divide-by-1 option : SYSCLK
4
4
CLKIN
The main advantage of choosing a divide-by-1 oscillator is that EMI is reduced. The harmonics of low-speed
resonators extend through less of the emissions spectrum than the harmonics of faster resonators. The
divide-by-1 provides the capability of reducing the resonator speed by four times, and this results in a steeper
decay of emissions produced by the oscillator.