參數(shù)資料
型號(hào)： TMS32C6411ZLZ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 73/119頁
文件大?。?/td> 1742K
代理商： TMS32C6411ZLZ
SPRS196H MARCH 2002 REVISED JULY 2004
73
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
INPUT AND OUTPUT CLOCKS (CONTINUED)
timing requirements for ECLKIN
§
(see Figure 19)
NO.
300
UNIT
MIN
7.5
MAX
1
tc(EKI)
tw(EKIH)
tw(EKIL)
tt(EKI)
tJ(EKI)
Cycle time, ECLKIN
16P
ns
2
Pulse duration, ECLKIN high
3.38
ns
3
Pulse duration, ECLKIN low
3.38
ns
4
Transition time, ECLKIN
2
ns
5
Period jitter, ECLKIN
0.02E
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 300 MHz, use P = 3.33 ns.
The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
§E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.
Minimum ECLKIN times are based on internal logic speed; the maximum useable speed of the EMIF may be lower due to AC timing requirements.
On the -300 device, 75-MHz operation is achievable if the requirements of the EMIF Device Speed section are met. Minimum ECLKIN cycle times
must
be met, even when ECLKIN is generated by an internal clock source.
ECLKIN
2
3
4
4
5
1
Figure 19. ECLKIN Timing
switching characteristics over recommended operating conditions for ECLKOUT1
§#||
(see Figure 20)
NO.
PARAMETER
300
UNIT
MIN
MAX
±
175
EH + 0.7
1
tJ(EKO1)
tw(EKO1H)
tw(EKO1L)
tt(EKO1)
td(EKIH-EKO1H)
td(EKIL-EKO1L)
§E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns.
#The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
||EH is the high period of E (EMIF input clock period) in ns and EL is the low period of E (EMIF input clock period) in ns.
This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
Period jitter, ECLKOUT1
0
ps
2
Pulse duration, ECLKOUT1 high
EH 0.7
ns
3
Pulse duration, ECLKOUT1 low
EL 0.7
EL + 0.7
ns
4
Transition time, ECLKOUT1
1
ns
5
Delay time, ECLKIN high to ECLKOUT1 high
1
8
ns
6
Delay time, ECLKIN low to ECLKOUT1 low
1
8
ns
1
5
6
2
3
ECLKIN
ECLKOUT1
4
4
Figure 20. ECLKOUT1 Timing
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