參數(shù)資料
型號： TMS320LF2402PZS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 66/115頁
文件大小： 1511K
代理商： TMS320LF2402PZS
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
66
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLOAD
IOL
CT
IOH
Output
Under
Test
50
Where:
IOL
IOH
VLOAD
CT
=
=
=
=
2 mA (all outputs)
300
μ
A (all outputs)
1.5 V
50-pF typical load-circuit capacitance
Figure 17. Test Load Circuit
signal transition levels
The data in this section is shown for the 3.3-V version. Note that some of the signals use different reference
voltages, see the recommended operating conditions table. Output levels are driven to a minimum logic-high
level of 2.4 V and to a maximum logic-low level of 0.8 V.
Figure 18 shows output levels.
0.4 V (VOL)
20%
2.4 V (VOH)
80%
Figure 18. Output Levels
Output transition times are specified as follows:
For a
high-to-low
transition
, the level at which the output is said to be no longer high is below 80% of the
total voltage range and lower and the level at which the output is said to be low is 20% of the total voltage
range and lower.
For a
low-to-high transition
, the level at which the output is said to be no longer low is 20% of the total voltage
range and higher and the level at which the output is said to be high is 80% of the total voltage range and
higher.
Figure 19 shows the input levels.
0.8 V (VIL)
10%
2.0 V (VIH)
90%
Figure 19. Input Levels
Input transition times are specified as follows:
For a
high-to-low transition
on an input signal, the level at which the input is said to be no longer high is 90%
of the total voltage range and lower and the level at which the input is said to be low is 10% of the total voltage
range and lower.
For a
low-to-high transition
on an input signal, the level at which the input is said to be no longer low is 10%
of the total voltage range and higher and the level at which the input is said to be high is 90% of the total
voltage range and higher.
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